soc/intel/dnv: Fix ACPI reporting of root port interrupt routing
pcie_port.asl defines an IRQM method that looks up legacy interrupt swizzling based on incoming interrupt "pin" A-D and root port number. Unfortunately the 8-bit root port number stored at offset 0x4F in the config space matches the device number, not the 1-8 scheme used in the LUT reported to the OS. Fix the case values to match the hardware. Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9 Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -120,7 +120,7 @@ Method (IRQM, 1, Serialized) {
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Switch (ToInteger (Arg0)) {
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/* PCIe Root Port 1 */
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Case (Package() { 1 }) {
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Case (Package() { 9 }) {
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If (PICM) {
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Return (IQAA)
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} Else {
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@ -129,7 +129,7 @@ Method (IRQM, 1, Serialized) {
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}
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/* PCIe Root Port 2 */
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Case (Package() { 2 }) {
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Case (Package() { 10 }) {
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If (PICM) {
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Return (IQBA)
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} Else {
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@ -138,7 +138,7 @@ Method (IRQM, 1, Serialized) {
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}
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/* PCIe Root Port 3 */
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Case (Package() { 3 }) {
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Case (Package() { 11 }) {
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If (PICM) {
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Return (IQCA)
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} Else {
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@ -147,7 +147,7 @@ Method (IRQM, 1, Serialized) {
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}
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/* PCIe Root Port 4 */
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Case (Package() { 4 }) {
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Case (Package() { 12 }) {
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If (PICM) {
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Return (IQDA)
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} Else {
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@ -156,7 +156,7 @@ Method (IRQM, 1, Serialized) {
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}
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/* PCIe Root Port 5 */
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Case (Package() { 5 }) {
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Case (Package() { 14 }) {
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If (PICM) {
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Return (IQEA)
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} Else {
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@ -165,7 +165,7 @@ Method (IRQM, 1, Serialized) {
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}
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/* PCIe Root Port 6 */
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Case (Package() { 6 }) {
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Case (Package() { 15 }) {
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If (PICM) {
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Return (IQFA)
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} Else {
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@ -174,7 +174,7 @@ Method (IRQM, 1, Serialized) {
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}
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/* PCIe Root Port 7 */
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Case (Package() { 7 }) {
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Case (Package() { 16 }) {
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If (PICM) {
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Return (IQGA)
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} Else {
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@ -183,7 +183,7 @@ Method (IRQM, 1, Serialized) {
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}
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/* PCIe Root Port 8 */
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Case (Package() { 8 }) {
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Case (Package() { 17 }) {
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If (PICM) {
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Return (IQHA)
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} Else {
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