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soc/intel/dnv: Fix ACPI reporting of root port interrupt routing 

pcie_port.asl defines an IRQM method that looks up legacy interrupt
swizzling based on incoming interrupt "pin" A-D and root port number.

Unfortunately the 8-bit root port number stored at offset 0x4F in the
config space matches the device number, not the 1-8 scheme used in
the LUT reported to the OS.

Fix the case values to match the hardware.

Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Stephen Douthit 2019-08-05 10:46:02 -04:00 committed by Patrick Georgi
parent aa6a8fb919
commit a51f490870
1 changed files with 8 additions and 8 deletions
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16
src/soc/intel/denverton_ns/acpi/pcie.asl
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@ -120,7 +120,7 @@ Method (IRQM, 1, Serialized) {
Switch (ToInteger (Arg0)) { Switch (ToInteger (Arg0)) {
/* PCIe Root Port 1 */ /* PCIe Root Port 1 */
Case (Package() { 1 }) { Case (Package() { 9 }) {
If (PICM) { If (PICM) {
Return (IQAA) Return (IQAA)
} Else { } Else {
@ -129,7 +129,7 @@ Method (IRQM, 1, Serialized) {
} }
/* PCIe Root Port 2 */ /* PCIe Root Port 2 */
Case (Package() { 2 }) { Case (Package() { 10 }) {
If (PICM) { If (PICM) {
Return (IQBA) Return (IQBA)
} Else { } Else {
@ -138,7 +138,7 @@ Method (IRQM, 1, Serialized) {
} }
/* PCIe Root Port 3 */ /* PCIe Root Port 3 */
Case (Package() { 3 }) { Case (Package() { 11 }) {
If (PICM) { If (PICM) {
Return (IQCA) Return (IQCA)
} Else { } Else {
@ -147,7 +147,7 @@ Method (IRQM, 1, Serialized) {
} }
/* PCIe Root Port 4 */ /* PCIe Root Port 4 */
Case (Package() { 4 }) { Case (Package() { 12 }) {
If (PICM) { If (PICM) {
Return (IQDA) Return (IQDA)
} Else { } Else {
@ -156,7 +156,7 @@ Method (IRQM, 1, Serialized) {
} }
/* PCIe Root Port 5 */ /* PCIe Root Port 5 */
Case (Package() { 5 }) { Case (Package() { 14 }) {
If (PICM) { If (PICM) {
Return (IQEA) Return (IQEA)
} Else { } Else {
@ -165,7 +165,7 @@ Method (IRQM, 1, Serialized) {
} }
/* PCIe Root Port 6 */ /* PCIe Root Port 6 */
Case (Package() { 6 }) { Case (Package() { 15 }) {
If (PICM) { If (PICM) {
Return (IQFA) Return (IQFA)
} Else { } Else {
@ -174,7 +174,7 @@ Method (IRQM, 1, Serialized) {
} }
/* PCIe Root Port 7 */ /* PCIe Root Port 7 */
Case (Package() { 7 }) { Case (Package() { 16 }) {
If (PICM) { If (PICM) {
Return (IQGA) Return (IQGA)
} Else { } Else {
@ -183,7 +183,7 @@ Method (IRQM, 1, Serialized) {
} }
/* PCIe Root Port 8 */ /* PCIe Root Port 8 */
Case (Package() { 8 }) { Case (Package() { 17 }) {
If (PICM) { If (PICM) {
Return (IQHA) Return (IQHA)
} Else { } Else {