mb/google/brya: Move gpio_pm settings for brya variants to baseboards
The factory versions (minor version 22) of cr50 FW have an issue with producing short interrupt pulses, which can be missed by the ADL PCH if autonomous GPIO power management is enabled, therefore instead of continually adding the setting to all the variants, move it to the baseboard instead. Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tim Wawrzynczak
Subrata Banik
parent
bf4592743c
commit
a52b9c3a40
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@ -22,17 +22,6 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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# This disables autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "SaGv" = "SaGv_Enabled"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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@ -22,17 +22,6 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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# This disables autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "SaGv" = "SaGv_Enabled"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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@ -71,6 +71,16 @@ chip soc/intel/alderlake
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# FIVR RFI Spread Spectrum 1.5%
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register "FivrSpreadSpectrum" = "FIVR_SS_1_5"
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# This disables autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses.
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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@ -75,6 +75,16 @@ chip soc/intel/alderlake
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# FIVR RFI Spread Spectrum 1.5%
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register "FivrSpreadSpectrum" = "FIVR_SS_1_5"
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# This disables autonomous GPIO power management, otherwise old cr50 FW
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# only supports short pulses and they can be missed by the PCH.
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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@ -1,14 +1,4 @@
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chip soc/intel/alderlake
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# This disables autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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device domain 0 on
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device ref dtt on
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chip drivers/intel/dptf
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@ -21,16 +21,6 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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# This disabled autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "SaGv" = "SaGv_Enabled"
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register "PsysPmax" = "143"
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register "TcssAuxOri" = "1"
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@ -21,16 +21,6 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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# This disabled autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "SaGv" = "SaGv_Enabled"
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register "PsysPmax" = "143"
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register "TcssAuxOri" = "1"
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@ -23,16 +23,6 @@ fw_config
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end
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chip soc/intel/alderlake
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# This disabled autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "SaGv" = "SaGv_Enabled"
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register "MaxDramSpeed" = "3733"
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# Acoustic settings
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@ -23,16 +23,6 @@ fw_config
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end
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chip soc/intel/alderlake
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# This disabled autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "SaGv" = "SaGv_Enabled"
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register "MaxDramSpeed" = "3733"
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# Acoustic settings
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@ -31,16 +31,6 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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# This disables autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "SaGv" = "SaGv_Enabled"
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register "CnviBtAudioOffload" = "true"
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# FIVR RFI Spread Spectrum 6%
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@ -31,16 +31,6 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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# This disables autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "SaGv" = "SaGv_Enabled"
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register "CnviBtAudioOffload" = "true"
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# FIVR RFI Spread Spectrum 6%
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@ -39,16 +39,6 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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# This disabled autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
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@ -39,16 +39,6 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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# This disabled autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
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@ -36,16 +36,6 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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# This disabled autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
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@ -22,18 +22,6 @@ fw_config
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end
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end
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chip soc/intel/alderlake
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# This disables autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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register "SaGv" = "SaGv_Enabled"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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