mb/intel/kblrvp: Add Variant board support for KBLRVP

Add support of Variant board model for existing intel/kblrvp,
since there might be more RVP board supports under
intel/kblrvp. Existing is for KBL RVP3 board.

BUG=none
BRANCH=none
TEST=Built and boot Kaby Lake RVP3

Change-Id: I041a07a273dbb77e422d48591f06b5f1011cd9f7
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/17630
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

src/Kconfig

@@ -326,7 +326,7 @@ config GENERIC_SPD_BIN
 
 config DIMM_MAX
 	int
-	default 2
+	default 4
 	depends on GENERIC_SPD_BIN
 	help
 	  Total number of memory DIMM slots available on motherboard.

src/mainboard/intel/kblrvp/Kconfig

@@ -48,6 +48,10 @@ config MAINBOARD_DIR
 	string
 	default "intel/kblrvp"
 
+config VARIANT_DIR
+	string
+	default "rvp3"
+
 config MAINBOARD_PART_NUMBER
 	string
 	default "Kblrvp"
@@ -68,4 +72,8 @@ config GBB_HWID
 	string
 	depends on CHROMEOS
 	default "KBLRVP TEST 8819"
+
+config DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
 endif

src/mainboard/intel/kblrvp/Makefile.inc

@@ -32,3 +32,6 @@ ramstage-y += mainboard.c
 ramstage-y += ramstage.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/intel/kblrvp/acpi/ec.asl

@@ -15,7 +15,7 @@
 
 /* mainboard configuration */
 #include "../ec.h"
-#include "../gpio.h"
+#include <variant/gpio.h>
 
 /* Enable EC backed ALS device in ACPI */
 #define EC_ENABLE_ALS_DEVICE

src/mainboard/intel/kblrvp/acpi/mainboard.asl

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include "../gpio.h"
+#include <variant/gpio.h>
 
 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 Scope (\_SB)

src/mainboard/intel/kblrvp/bootblock.c

@@ -15,7 +15,7 @@
 
 #include <bootblock_common.h>
 #include <soc/gpio.h>
-#include "gpio.h"
+#include <variant/gpio.h>
 
 static void early_config_gpio(void)
 {

src/mainboard/intel/kblrvp/mainboard.c

@@ -24,7 +24,7 @@
 #include <soc/nhlt.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
-#include "gpio.h"
+#include <variant/gpio.h>
 
 static void mainboard_init(device_t dev)
 {

src/mainboard/intel/kblrvp/ramstage.c

@@ -17,7 +17,7 @@
 #include <console/console.h>
 #include <device/i2c.h>
 #include <soc/ramstage.h>
-#include "gpio.h"
+#include <variant/gpio.h>
 
 void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {

src/mainboard/intel/kblrvp/smihandler.c

@@ -25,7 +25,7 @@
 #include <soc/pm.h>
 #include <soc/smm.h>
 #include "ec.h"
-#include "gpio.h"
+#include <variant/gpio.h>
 
 int mainboard_io_trap_handler(int smif)
 {

src/mainboard/intel/kblrvp/spd/spd.h

@@ -18,8 +18,7 @@
 #define MAINBOARD_SPD_H
 
 #include <gpio.h>
-#include "../gpio.h"
+#include <variant/gpio.h>
-
 
 #define RCOMP_TARGET_PARAMS	0x5