mb/intel/kblrvp: Use common lib spd_bin to get spd
Use common lib spd_bin to get spd. Change-Id: If94413fc36a98f7694f560955bbb80abefe32166 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select SOC_INTEL_SKYLAKE
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select MAINBOARD_USES_FSP2_0
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select MAINBOARD_HAS_CHROMEOS
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select GENERIC_SPD_BIN
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config CHROMEOS
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select LID_SWITCH
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@ -23,20 +23,33 @@
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#include <soc/gpio.h>
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#include "spd/spd.h"
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#include <string.h>
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#include <spd_bin.h>
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#include "board_id.h"
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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FSP_M_CONFIG *mem_cfg;
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mem_cfg = &mupd->FspmConfig;
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struct region_device spd_rdev;
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u8 spd_index = (get_board_id() >> 5) & 0x7;
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printk(BIOS_INFO, "SPD index %d\n", spd_index);
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mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
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mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
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mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
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mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
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/* RVP3 SPD */
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mem_cfg->DqPinsInterleaved = 0;
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mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
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if (mainboard_has_dual_channel_mem())
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mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
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mem_cfg->MemorySpdDataLen = SPD_LEN;
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if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) {
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die("spd.bin not found\n");
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}
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mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
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/* Memory leak is ok since we have memory mapped boot media */
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mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
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mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
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}
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@ -26,17 +26,3 @@ SPD_SOURCES += empty # 4b100
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SPD_SOURCES += empty # 5b101
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SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR # 6b110 Dual Channel 8GB
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SPD_SOURCES += empty # 7b111
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
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# Include spd ROM data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do printf $$(printf '\%o' 0x$$c); \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := spd
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@ -1,94 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/byteorder.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <soc/pei_data.h>
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#include <soc/romstage.h>
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#include <string.h>
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#include "spd.h"
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static void mainboard_print_spd_info(uint8_t spd[])
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{
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const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
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const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
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const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
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const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
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const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
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const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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char spd_name[SPD_PART_LEN+1] = { 0 };
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int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
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int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
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int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
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int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
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int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
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int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
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int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
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/* Module type */
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printk(BIOS_INFO, "SPD: module type is ");
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switch (spd[SPD_DRAM_TYPE]) {
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case SPD_DRAM_DDR3:
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printk(BIOS_INFO, "DDR3\n");
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break;
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case SPD_DRAM_LPDDR3:
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case SPD_DRAM_LPDDR3_INTEL:
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printk(BIOS_INFO, "LPDDR3\n");
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break;
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default:
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printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
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break;
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}
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/* Module Part Number */
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memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
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spd_name[SPD_PART_LEN] = 0;
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printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
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printk(BIOS_INFO,
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"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
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banks, ranks, rows, cols, capmb);
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printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
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devw, busw);
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if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
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/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
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printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
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capmb / 8 * busw / devw * ranks);
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}
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}
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/* Copy SPD data for on-board memory */
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void mainboard_fill_spd_data(struct pei_data *pei_data)
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{
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uintptr_t spd_data;
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spd_data = mainboard_get_spd_data();
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memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN);
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if (mainboard_has_dual_channel_mem())
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memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN);
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/* Make sure a valid SPD was found */
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if (pei_data->spd_data[0][0][0] == 0)
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die("Invalid SPD data.");
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mainboard_print_spd_info(pei_data->spd_data[0][0]);
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}
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@ -15,25 +15,11 @@
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*/
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#ifndef MAINBOARD_SPD_H
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#define MAINBOARD_SPD_H
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#include <gpio.h>
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#include "../gpio.h"
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#define MAINBOARD_SPD_H
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#define SPD_LEN 256
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0B
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#define SPD_DRAM_LPDDR3 0x0F
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#define SPD_DRAM_LPDDR3_INTEL 0xF1
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_ORGANIZATION 7
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#define SPD_BUS_DEV_WIDTH 8
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#define SPD_PART_OFF 128
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#define SPD_PART_LEN 18
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#define SPD_MANU_OFF 148
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#define RCOMP_TARGET_PARAMS 0x5
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@ -41,6 +27,4 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr);
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void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
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void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
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void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
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uintptr_t mainboard_get_spd_data(void);
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int mainboard_has_dual_channel_mem(void);
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#endif
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@ -58,37 +58,3 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
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memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
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}
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uintptr_t mainboard_get_spd_data(void)
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{
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char *spd_file;
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int spd_index, spd_span;
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size_t spd_file_len;
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spd_index = (get_board_id() >> 5) & 0xF;
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printk(BIOS_INFO, "SPD index %d\n", spd_index);
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/* Load SPD data from CBFS */
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spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
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&spd_file_len);
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if (!spd_file)
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die("SPD data not found.");
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/* make sure we have at least one SPD in the file. */
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if (spd_file_len < SPD_LEN)
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die("Missing SPD data.");
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/* Make sure we did not overrun the buffer */
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if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
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printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
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spd_index = 0;
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}
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spd_span = spd_index * SPD_LEN;
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return (uintptr_t)(spd_file + spd_span);
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}
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int mainboard_has_dual_channel_mem(void)
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{
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return 1;
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}
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