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Update gpp port configuration. 

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan 2011-05-15 22:07:56 +00:00 committed by Marc Jones
parent 769527e523
commit a64ab46b62
3 changed files with 14 additions and 18 deletions
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14
src/mainboard/amd/persimmon/devicetree.cb
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@ -81,13 +81,13 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
end end
end # f81865f end # f81865f
end #LPC end #LPC
device pci 14.4 on end # PCI 0x4384 device pci 14.4 on end # PCI 0x4384
device pci 14.5 on end # USB 2 device pci 14.5 on end # USB 2
device pci 15.0 on end # PCIe PortA device pci 15.0 off end # PCIe PortA
device pci 15.1 on end # PCIe PortB device pci 15.1 off end # PCIe PortB
device pci 15.2 on end # PCIe PortC device pci 15.2 off end # PCIe PortC
device pci 15.3 on end # PCIe PortD device pci 15.3 off end # PCIe PortD
register "gpp_configuration" = "4" #1:1:1:1 register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx_wrapper/sb800 end #southbridge/amd/cimx_wrapper/sb800
# end # device pci 18.0 # end # device pci 18.0

4
src/southbridge/amd/cimx_wrapper/sb800/cfg.c
View File

@ -99,10 +99,6 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
sb_config->GppFunctionEnable = GPP_CONTROLLER; sb_config->GppFunctionEnable = GPP_CONTROLLER;
sb_config->GppLinkConfig = GPP_CFGMODE; sb_config->GppLinkConfig = GPP_CFGMODE;
//sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE; //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
sb_config->PORTCONFIG[0].PortCfg.PortPresent = ENABLED;
sb_config->PORTCONFIG[1].PortCfg.PortPresent = ENABLED;
sb_config->PORTCONFIG[2].PortCfg.PortPresent = ENABLED;
sb_config->PORTCONFIG[3].PortCfg.PortPresent = ENABLED;
sb_config->GppUnhidePorts = TRUE; //visable always, even port empty sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
//sb_config->NbSbGen2 = TRUE; //sb_config->NbSbGen2 = TRUE;
//sb_config->GppGen2 = TRUE; //sb_config->GppGen2 = TRUE;

14
src/southbridge/amd/cimx_wrapper/sb800/late.c
View File

@ -315,7 +315,6 @@ static const struct pci_driver PORTD_driver __pci_driver = {
*/ */
static void sb800_enable(device_t dev) static void sb800_enable(device_t dev)
{ {
u8 gpp_port = 0;
struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip = struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
(struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info); (struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
@ -414,15 +413,16 @@ static void sb800_enable(device_t dev)
break; break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
return;
case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */ case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
return;
case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */ case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
return;
case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */ case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
gpp_port = (dev->path.pci.devfn) & 0x03; sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
if (dev->enabled) {
sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
} else {
sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
}
/* /*
* GPP_CFGMODE_X4000: PortA Lanes[3:0] * GPP_CFGMODE_X4000: PortA Lanes[3:0]