Update gpp port configuration.
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -81,13 +81,13 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
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end
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end # f81865f
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end #LPC
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device pci 14.4 on end # PCI 0x4384
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device pci 14.5 on end # USB 2
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device pci 15.0 on end # PCIe PortA
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device pci 15.1 on end # PCIe PortB
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device pci 15.2 on end # PCIe PortC
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device pci 15.3 on end # PCIe PortD
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register "gpp_configuration" = "4" #1:1:1:1
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device pci 14.4 on end # PCI 0x4384
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device pci 14.5 on end # USB 2
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device pci 15.0 off end # PCIe PortA
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device pci 15.1 off end # PCIe PortB
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device pci 15.2 off end # PCIe PortC
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device pci 15.3 off end # PCIe PortD
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register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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end #southbridge/amd/cimx_wrapper/sb800
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# end # device pci 18.0
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@ -99,10 +99,6 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
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sb_config->GppFunctionEnable = GPP_CONTROLLER;
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sb_config->GppLinkConfig = GPP_CFGMODE;
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//sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
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sb_config->PORTCONFIG[0].PortCfg.PortPresent = ENABLED;
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sb_config->PORTCONFIG[1].PortCfg.PortPresent = ENABLED;
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sb_config->PORTCONFIG[2].PortCfg.PortPresent = ENABLED;
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sb_config->PORTCONFIG[3].PortCfg.PortPresent = ENABLED;
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sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
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//sb_config->NbSbGen2 = TRUE;
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//sb_config->GppGen2 = TRUE;
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@ -315,7 +315,6 @@ static const struct pci_driver PORTD_driver __pci_driver = {
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*/
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static void sb800_enable(device_t dev)
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{
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u8 gpp_port = 0;
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struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
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(struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
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@ -414,15 +413,16 @@ static void sb800_enable(device_t dev)
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break;
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case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
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sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
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return;
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case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
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sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
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return;
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case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
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sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
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return;
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case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
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gpp_port = (dev->path.pci.devfn) & 0x03;
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if (dev->enabled) {
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sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
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} else {
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sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
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}
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sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
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/*
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* GPP_CFGMODE_X4000: PortA Lanes[3:0]
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