soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to ME_RW_A/B regions. On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B regions. FMAP REGION: ME_RW_A Name Offset Type Size Comp me_rw 0x0 raw 1275246 LZMA (1957888 decompressed) (empty) 0x1375c0 null 193056 none FMAP REGION: ME_RW_B Name Offset Type Size Comp me_rw 0x0 raw 1275246 LZMA (1957888 decompressed) (empty) 0x1375c0 null 193056 none Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -150,6 +150,13 @@ config SOC_INTEL_CSE_NPHY_CBFS_FILE
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help
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help
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CBFS path and file name for Intel CSE sub-partition NPHY binary
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CBFS path and file name for Intel CSE sub-partition NPHY binary
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config SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
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bool
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default n
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depends on SOC_INTEL_CSE_LITE_SKU
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help
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Enable compression on Intel CSE CBFS RW blob
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if STITCH_ME_BIN
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if STITCH_ME_BIN
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config CSE_COMPONENTS_PATH
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config CSE_COMPONENTS_PATH
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@ -85,6 +85,9 @@ cbfs-files-y += $(CSE_LITE_ME_RW)
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$(CSE_LITE_ME_RW)-file := $(CSE_RW_FILE)
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$(CSE_LITE_ME_RW)-file := $(CSE_RW_FILE)
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$(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW)
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$(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW)
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$(CSE_LITE_ME_RW)-type := raw
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$(CSE_LITE_ME_RW)-type := raw
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ifeq ($(CONFIG_SOC_INTEL_CSE_LITE_COMPRESS_ME_RW),y)
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$(CSE_LITE_ME_RW)-compression := LZMA
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endif
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$(obj)/cse_rw.version:
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$(obj)/cse_rw.version:
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@echo '$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION))' > $@
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@echo '$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION))' > $@
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