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Krishna Prasad Bhat a67a92e3c0 soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on
ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to
ME_RW_A/B regions.

On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B
regions.

FMAP REGION: ME_RW_A
Name                           Offset     Type           Size   Comp
me_rw                          0x0        raw           1275246 LZMA
(1957888 decompressed)
(empty)                        0x1375c0   null           193056 none

FMAP REGION: ME_RW_B
Name                           Offset     Type           Size   Comp
me_rw                          0x0        raw           1275246 LZMA
(1957888 decompressed)
(empty)                        0x1375c0   null           193056 none

Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 14:21:57 +00:00
3rdparty Update fsp submodule to upstream master 2022-03-01 01:53:17 +00:00
Documentation mb/starlabs/labtop: Add LabTop Mk IV 2022-03-08 16:05:46 +00:00
LICENSES treewide: Remove trailing whitespace 2021-02-17 17:30:05 +00:00
configs src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard 2022-02-11 20:14:55 +00:00
payloads payloads/tianocore: Add prompt for Boot Timeout 2022-03-09 14:20:30 +00:00
spd util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) 2022-03-08 23:46:50 +00:00
src soc/intel/common: Add Kconfig to enable compression on ME_RW blobs 2022-03-09 14:21:57 +00:00
tests coreboot_tables.c: Expose the ACPI RSDP 2022-03-09 14:21:01 +00:00
util cbfstool/linux_trampoline: Fill the ACPI RSDP entry 2022-03-09 14:21:26 +00:00
.checkpatch.conf lint: checkpatch: Only exclude specific src/vendorcode/ subdirectories 2021-04-06 16:04:41 +00:00
.clang-format
.editorconfig
.gitignore .gitignore: Ignore .test/.dependencies globally 2020-10-31 18:21:36 +00:00
.gitmodules .gitmodules: Update intel-microcode submodule to track branch=main 2021-06-09 17:20:50 +00:00
.gitreview
.mailmap .mailmap: Add a .mailmap file for git 2022-03-08 18:53:47 +00:00
AUTHORS AUTHORS, util/: Drop individual copyright notices 2020-05-09 21:21:32 +00:00
COPYING
MAINTAINERS MAINTAINERS: Update INTEL DENVERTON-NS SOC & HARCUVAR CRB Maintainers 2022-03-08 15:04:45 +00:00
Makefile Makefile: Add .SECONDARY 2022-02-28 22:00:42 +00:00
Makefile.inc Makefile: Add a build target for .map 2022-02-28 22:00:55 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
gnat.adc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
toolchain.inc build system: immediately report what users are supposed to look into 2021-10-18 16:39:25 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.