Fix whitespace in tyan s289{1,2,5} files. Also removes some #if 0 and #if 1
that don't seem to clarify anything. Abuild tested. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
297b91c6cd
commit
a67c354cbf
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@ -54,24 +54,20 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
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end
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else
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makerule ./auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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else
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else
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##
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## Romcc output
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##
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@ -107,7 +103,6 @@ end
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mainboardinit cpu/x86/32bit/entry32.inc
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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@ -195,7 +190,6 @@ else
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end
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##
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## Include the secondary Configuration files
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##
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@ -203,7 +197,6 @@ if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s2891
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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@ -211,7 +204,6 @@ chip northbridge/amd/amdk8/root_complex
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8 #mc0
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device pci 18.0 on # northbridge
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@ -351,6 +343,7 @@ chip northbridge/amd/amdk8/root_complex
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end #mc0
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end # pci_domain
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 off end # pci_regs_all
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@ -30,9 +30,9 @@ uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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uses COREBOOT_EXTRA_VERSION
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@ -75,7 +75,6 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
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uses CONFIG_LB_MEM_TOPK
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## ROM_SIZE is the size of boot ROM that this board will use.
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#512K bytes
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default ROM_SIZE=524288
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@ -83,7 +82,6 @@ default ROM_SIZE=524288
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#1M bytes
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#default ROM_SIZE=1048576
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##
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## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
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##
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@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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}
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#define QRANK_DIMM_SUPPORT 1
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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@ -123,8 +122,6 @@ static void main(unsigned long bist)
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k8_init_and_stop_secondaries();
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}
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// post_code(0x32);
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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@ -8,7 +8,6 @@
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#define SET_NB_CFG_54 1
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#endif
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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@ -21,17 +20,6 @@
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#if 0
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static void post_code(uint8_t value) {
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#if 1
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int i;
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for(i=0;i<0x80000;i++) {
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outb(value, 0x80);
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}
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#endif
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}
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#endif
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#include <cpu/amd/model_fxx_rev.h>
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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@ -54,7 +42,6 @@ static void post_code(uint8_t value) {
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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static void memreset_setup(void)
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{
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}
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@ -92,7 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/model_fxx/init_cpus.c"
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#if USE_FALLBACK_IMAGE == 1
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#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
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@ -91,7 +91,6 @@ static unsigned long main(unsigned long bist)
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: "a" (bist) /* inputs */
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: /* clobbers */
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);
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fallback_image:
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return bist;
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}
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@ -62,9 +62,9 @@ void get_bus_conf(void)
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{
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unsigned apicid_base;
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unsigned sbdn;
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device_t dev;
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unsigned sbdn;
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int i;
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if(get_bus_conf_done==1) return; //do it only once
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@ -91,51 +91,15 @@ void get_bus_conf(void)
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dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
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if (dev) {
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bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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#if 0
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bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804_2++;
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#else
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bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804_4++;
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#endif
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}
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else {
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printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
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bus_ck804_1 = 2;
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#if 0
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bus_ck804_2 = 3;
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#else
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bus_ck804_4 = 3;
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#endif
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}
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#if 0
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dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
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if (dev) {
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bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804_3++;
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}
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else {
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printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
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bus_ck804_3 = bus_ck804_2+1;
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}
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dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
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if (dev) {
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bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804_4++;
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}
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else {
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printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
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bus_ck804_4 = bus_ck804_3+1;
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}
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#endif
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dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
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if (dev) {
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@ -160,7 +124,6 @@ void get_bus_conf(void)
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}
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bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
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/* 8131-1 */
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dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
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if (dev) {
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@ -54,10 +54,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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struct irq_info *pirq_info;
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unsigned slot_num;
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uint8_t *v;
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unsigned sbdn;
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uint8_t sum=0;
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int i;
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unsigned sbdn;
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get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
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sbdn = sysconf.sbdn;
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@ -6,7 +6,6 @@
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static void setup_s2891_resource_map(void)
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{
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static const unsigned int register_values[] = {
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#if 1
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/* Careful set limit registers before base registers which contain the enables */
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/* DRAM Limit i Registers
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* F1:0x44 i = 0
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@ -80,8 +79,6 @@ static void setup_s2891_resource_map(void)
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PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
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#endif
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#if 1
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/* Memory-Mapped I/O Limit i Registers
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* F1:0x84 i = 0
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@ -158,8 +155,6 @@ static void setup_s2891_resource_map(void)
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PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
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// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
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#endif
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#if 1
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/* PCI I/O Limit i Registers
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* F1:0xC4 i = 0
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@ -220,7 +215,7 @@ static void setup_s2891_resource_map(void)
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PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
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#endif
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/* Config Base and Limit i Registers
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* F1:0xE0 i = 0
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* F1:0xE4 i = 1
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@ -257,12 +252,10 @@ static void setup_s2891_resource_map(void)
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* [31:24] Bus Number Limit i
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* This field defines the highest bus number in configuration region i
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*/
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#if 1
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// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
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// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
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PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
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#endif
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};
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@ -43,10 +43,10 @@ arch i386 end
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driver mainboard.o
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#dir /drivers/ati/ragexl
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#needed by irq_tables and mptable and acpi_tables
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object get_bus_conf.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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@ -54,24 +54,20 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
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end
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else
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makerule ./auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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else
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else
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##
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## Romcc output
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##
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@ -89,12 +85,12 @@ makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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end
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##
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@ -202,7 +198,6 @@ if CONFIG_CHIP_NAME
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config chip.h
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end
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# sample config for tyan/s2892
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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@ -210,7 +205,6 @@ chip northbridge/amd/amdk8/root_complex
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8 #mc0
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device pci 18.0 on # northbridge
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@ -30,9 +30,9 @@ uses USE_OPTION_TABLE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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uses COREBOOT_EXTRA_VERSION
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@ -76,7 +76,6 @@ default ROM_SIZE=524288
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#1M bytes
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#default ROM_SIZE=1048576
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##
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## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
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##
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@ -131,6 +130,9 @@ default CONFIG_MAX_CPUS=4
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default CONFIG_MAX_PHYSICAL_CPUS=2
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default CONFIG_LOGICAL_CPUS=1
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#1G memory hole
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default HW_MEM_HOLE_SIZEK=0x100000
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##HT Unit ID offset, default is 1, the typical one
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default HT_CHAIN_UNITID_BASE=0x0
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@ -143,9 +145,6 @@ default SB_HT_CHAIN_ON_BUS0=2
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##only offset for SB chain?, default is yes(1)
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default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
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#1G memory hole
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default HW_MEM_HOLE_SIZEK=0x100000
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#BTEXT Console
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#default CONFIG_CONSOLE_BTEXT=1
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@ -91,7 +91,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "southbridge/nvidia/ck804/ck804_early_setup.c"
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static void main(unsigned long bist)
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{
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static const struct mem_controller cpu[] = {
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@ -125,7 +124,6 @@ static void main(unsigned long bist)
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k8_init_and_stop_secondaries();
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}
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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@ -13,18 +13,8 @@
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#if 0
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static void post_code(uint8_t value) {
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#if 1
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int i;
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for(i=0;i<0x80000;i++) {
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outb(value, 0x80);
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}
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#endif
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}
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#endif
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#include <cpu/amd/model_fxx_rev.h>
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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@ -96,7 +86,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "cpu/amd/model_fxx/init_cpus.c"
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#if USE_FALLBACK_IMAGE == 1
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|
||||
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
|
||||
|
@ -118,6 +107,7 @@ static void sio_setup(void)
|
|||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
|
||||
|
||||
}
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
|
@ -180,7 +170,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
|
||||
static const uint16_t spd_addr [] = {
|
||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
||||
|
|
|
@ -88,51 +88,15 @@ void get_bus_conf(void)
|
|||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_4 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
|
||||
if (dev) {
|
||||
|
@ -157,7 +121,6 @@ void get_bus_conf(void)
|
|||
}
|
||||
|
||||
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
|
||||
if (dev) {
|
||||
|
|
|
@ -22,6 +22,7 @@ extern unsigned apicid_8131_2;
|
|||
|
||||
extern unsigned sbdn3;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
|
|
|
@ -6,7 +6,6 @@
|
|||
static void setup_s2892_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
#if 1
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
|
@ -80,8 +79,6 @@ static void setup_s2892_resource_map(void)
|
|||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
#endif
|
||||
#if 1
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
|
@ -158,8 +155,6 @@ static void setup_s2892_resource_map(void)
|
|||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
#endif
|
||||
#if 1
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
|
@ -220,7 +215,7 @@ static void setup_s2892_resource_map(void)
|
|||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
#endif
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
|
@ -257,12 +252,10 @@ static void setup_s2892_resource_map(void)
|
|||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration region i
|
||||
*/
|
||||
#if 1
|
||||
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
|
||||
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
|
|
|
@ -59,6 +59,7 @@ object get_bus_conf.o
|
|||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#object reset.o
|
||||
|
||||
if USE_DCACHE_RAM
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
@ -128,7 +129,6 @@ if USE_DCACHE_RAM
|
|||
end
|
||||
end
|
||||
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
|
@ -243,7 +243,7 @@ chip northbridge/amd/amdk8/root_complex
|
|||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8 #mc0
|
||||
device pci 18.0 on
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/nvidia/ck804
|
||||
device pci 0.0 on end # HT
|
||||
|
@ -313,25 +313,6 @@ chip northbridge/amd/amdk8/root_complex
|
|||
end
|
||||
end # SM
|
||||
device pci 1.1 on # SM 1
|
||||
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
|
||||
# chip drivers/generic/generic #PCIXA Slot1
|
||||
# device i2c 50 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCIXB Slot1
|
||||
# device i2c 51 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCIXB Slot2
|
||||
# device i2c 52 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCI Slot1
|
||||
# device i2c 53 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #Master CK804 PCI-E
|
||||
# device i2c 54 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #Slave CK804 PCI-E
|
||||
# device i2c 55 on end
|
||||
# end
|
||||
chip drivers/generic/generic #MAC EEPROM
|
||||
device i2c 51 on end
|
||||
end
|
||||
|
|
|
@ -166,7 +166,7 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
|
|||
#Opteron K8 1G HT Support
|
||||
default K8_HT_FREQ_1G_SUPPORT=1
|
||||
|
||||
#VGA
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
|
|
|
@ -71,13 +71,9 @@ static void sio_gpio_setup(void){
|
|||
unsigned value;
|
||||
|
||||
// lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
|
||||
|
||||
#if 1
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
|
||||
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
|
@ -91,22 +87,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
}
|
||||
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#if 0
|
||||
#define ENABLE_APIC_EXT_ID 1
|
||||
#define APIC_ID_OFFSET 0x10
|
||||
#define LIFT_BSP_APIC_ID 0
|
||||
#else
|
||||
#define ENABLE_APIC_EXT_ID 0
|
||||
#endif
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
/* tyan does not want the default */
|
||||
#include "resourcemap.c"
|
||||
|
||||
|
||||
#define FIRST_CPU 1
|
||||
#define SECOND_CPU 1
|
||||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||
|
@ -116,7 +103,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#define CK804_USE_NIC 1
|
||||
#define CK804_USE_ACI 1
|
||||
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
|
||||
|
||||
//set GPIO to input mode
|
||||
#define CK804_MB_SETUP \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
|
||||
|
@ -128,7 +114,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
|
||||
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
|
||||
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
|
@ -162,8 +147,6 @@ static void main(unsigned long bist)
|
|||
k8_init_and_stop_secondaries();
|
||||
}
|
||||
|
||||
// post_code(0x32);
|
||||
|
||||
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
@ -186,11 +169,9 @@ static void main(unsigned long bist)
|
|||
soft_reset();
|
||||
}
|
||||
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
|
||||
|
||||
}
|
||||
|
|
|
@ -1,18 +1,16 @@
|
|||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
|
||||
#define K8_ALLOCATE_IO_RANGE 1
|
||||
//#define K8_SCAN_PCI_BUS 1
|
||||
|
||||
|
||||
//used by raminit
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#define SET_NB_CFG_54 1
|
||||
#endif
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
|
@ -27,17 +25,6 @@
|
|||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
|
||||
#if 0
|
||||
static void post_code(uint8_t value) {
|
||||
#if 1
|
||||
int i;
|
||||
for(i=0;i<0x8000;i++) {
|
||||
outb(value, 0x80);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
|
@ -68,7 +55,6 @@ static void post_code(uint8_t value) {
|
|||
|
||||
#include "cpu/amd/mtrr/amd_earlymtrr.c"
|
||||
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
|
||||
|
@ -81,7 +67,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
|
|||
{
|
||||
}
|
||||
|
||||
|
||||
static void sio_gpio_setup(void){
|
||||
|
||||
unsigned value;
|
||||
|
@ -103,7 +88,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
@ -144,7 +128,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
|
||||
static void sio_setup(void)
|
||||
{
|
||||
|
||||
|
@ -152,7 +135,6 @@ static void sio_setup(void)
|
|||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
|
||||
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
|
||||
|
||||
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
|
||||
|
@ -227,6 +209,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
|
@ -234,15 +217,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
#if HAVE_FAILOVER_BOOT==1
|
||||
#if USE_FAILOVER_IMAGE==1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#else
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
#else
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
|
||||
}
|
||||
|
||||
#if USE_FAILOVER_IMAGE==0
|
||||
|
|
|
@ -50,14 +50,12 @@ static void sio_setup(void)
|
|||
|
||||
}
|
||||
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include "cpu/amd/dualcore/dualcore_id.c"
|
||||
#else
|
||||
#include "cpu/amd/model_fxx/node_id.c"
|
||||
#endif
|
||||
|
||||
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
/* Is this a cpu only reset? */
|
||||
|
|
|
@ -9,7 +9,6 @@
|
|||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
|
||||
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
|
||||
//busnum is default
|
||||
unsigned char bus_isa;
|
||||
|
@ -56,6 +55,7 @@ unsigned hcdnx[] =
|
|||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
};
|
||||
|
||||
unsigned sbdn3;
|
||||
unsigned sbdnb;
|
||||
|
||||
|
@ -97,63 +97,15 @@ void get_bus_conf(void)
|
|||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_5 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
|
||||
|
||||
bus_ck804_5 = bus_ck804_4+1;
|
||||
}
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
|
||||
if (dev) {
|
||||
|
@ -194,56 +146,6 @@ void get_bus_conf(void)
|
|||
|
||||
if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed
|
||||
bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff;
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x09);
|
||||
|
||||
bus_ck804b_1 = bus_ck804b_0+1;
|
||||
bus_ck804b_2 = bus_ck804b_0+2;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0b);
|
||||
|
||||
bus_ck804b_2 = bus_ck804b_0+1;
|
||||
bus_ck804b_3 = bus_ck804b_0+2;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0c);
|
||||
|
||||
bus_ck804b_4 = bus_ck804b_3+1;
|
||||
}
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0d);
|
||||
|
||||
bus_ck804b_5 = bus_ck804b_4+1;
|
||||
}
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0));
|
||||
if (dev) {
|
||||
|
@ -253,10 +155,7 @@ void get_bus_conf(void)
|
|||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
|
||||
#if 1
|
||||
bus_ck804b_5 = bus_ck804b_4+1;
|
||||
#endif
|
||||
|
||||
bus_isa = bus_ck804b_5+1;
|
||||
}
|
||||
}
|
||||
|
@ -272,5 +171,4 @@ void get_bus_conf(void)
|
|||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
apicid_ck804b = apicid_base+3;
|
||||
|
||||
}
|
||||
|
|
|
@ -50,6 +50,8 @@ extern unsigned char bus_ck804b_5;//f
|
|||
extern unsigned sbdn3;
|
||||
extern unsigned sbdnb;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
|
|
|
@ -30,6 +30,8 @@ extern unsigned apicid_ck804b;
|
|||
extern unsigned sbdn3;
|
||||
extern unsigned sbdnb;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
|
|
Loading…
Reference in New Issue