google/gru: Add a stub rk3399 mainboard
Most things still need to be filled in, but this will allow us to build boards which use this SOC. [pg: separated out from the combined commit that added both SoC and board. Added board_info.txt that will be added downstream, too.] Change-Id: I7facce7b98a5d19fb77746b1aee67fff74da8150 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840 Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332385 Reviewed-on: https://review.coreboot.org/14279 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
parent
3b42119237
commit
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2016 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config BOARD_GOOGLE_GRU # Umbrella option to be selected by variant boards.
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def_bool n
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if BOARD_GOOGLE_GRU
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ID_AUTO
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select BOARD_ROMSIZE_KB_8192
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select COMMON_CBFS_SPI_WRAPPER
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select HAVE_HARD_RESET
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select MAINBOARD_HAS_CHROMEOS
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select SOC_ROCKCHIP_RK3399
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select SPI_FLASH
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select SPI_FLASH_GIGADEVICE
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select SPI_FLASH_WINBOND
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config CHROMEOS
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select CHROMEOS_VBNV_FLASH
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select VBOOT2_MOCK_SECDATA
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select VIRTUAL_DEV_SWITCH
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config MAINBOARD_DIR
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string
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default google/gru
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config MAINBOARD_PART_NUMBER
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string
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default "Gru"
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config MAINBOARD_VENDOR
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string
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default "Google"
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config DRAM_SIZE_MB
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int
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default 2048
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 0
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config BOOT_MEDIA_SPI_BUS
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int
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default 1
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config CONSOLE_SERIAL_UART_ADDRESS
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hex
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depends on DRIVERS_UART
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default 0xFF1A0000
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endif # BOARD_GOOGLE_GRU
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config BOARD_GOOGLE_KEVIN
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bool "Kevin"
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select BOARD_GOOGLE_GRU
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2016 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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bootblock-y += boardid.c
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bootblock-y += bootblock.c
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bootblock-y += chromeos.c
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bootblock-y += memlayout.ld
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bootblock-y += reset.c
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verstage-y += boardid.c
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verstage-y += chromeos.c
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verstage-y += memlayout.ld
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verstage-y += memlayout.ld
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verstage-y += reset.c
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romstage-y += boardid.c
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romstage-y += chromeos.c
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romstage-y += memlayout.ld
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romstage-y += reset.c
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romstage-y += romstage.c
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ramstage-y += boardid.c
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ramstage-y += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += memlayout.ld
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ramstage-y += reset.c
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Vendor name: Google
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Board name: Gru Rockchip RK3399 reference board
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Category: eval
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boardid.h>
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#include <console/console.h>
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#include <stdlib.h>
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uint8_t board_id(void)
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{
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return 0;
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}
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uint32_t ram_code(void)
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{
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return 0;
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <bootblock_common.h>
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void bootblock_mainboard_early_init(void)
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{
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}
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void bootblock_mainboard_init(void)
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{
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <boot/coreboot_tables.h>
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#include <console/console.h>
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#include <ec/google/chromeec/ec.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include <string.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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}
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int get_developer_mode_switch(void)
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{
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return 0;
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}
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int get_recovery_mode_switch(void)
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{
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return 0;
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}
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int get_write_protect_state(void)
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{
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return 0;
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}
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FLASH@0x0 0x800000 {
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WP_RO@0x0 0x400000 {
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RO_SECTION@0x0 0x3e0000 {
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BOOTBLOCK@0 128K
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COREBOOT(CBFS)@0x20000 0x2e0000
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FMAP@0x300000 0x1000
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GBB@0x301000 0xdef00
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RO_FRID@0x3dff00 0x100
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}
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RO_VPD@0x3e0000 0x20000
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}
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RW_SECTION_A@0x400000 0xe8000 {
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VBLOCK_A@0x0 0x2000
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FW_MAIN_A(CBFS)@0x2000 0xe5f00
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RW_FWID_A@0xe7f00 0x100
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}
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RW_VPD@0x4e8000 0x8000
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RW_SECTION_B@0x4f0000 0xe8000 {
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VBLOCK_B@0x0 0x2000
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FW_MAIN_B(CBFS)@0x2000 0xe5f00
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RW_FWID_B@0xe7f00 0x100
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}
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RW_ELOG@0x5d8000 0x8000
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RW_SHARED@0x5e0000 0x10000 {
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SHARED_DATA@0x0 0x10000
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}
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RW_NVRAM@0x5f0000 0x10000
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RW_LEGACY@0x600000 0x200000
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}
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##
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## This file is part of the coreboot project.
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##
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## Copyright 2016 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip soc/rockchip/rk3399
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device cpu_cluster 0 on end
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end
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <arch/cache.h>
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#include <arch/io.h>
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#include <boardid.h>
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#include <boot/coreboot_tables.h>
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#include <device/device.h>
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#include <console/console.h>
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static void mainboard_init(device_t dev)
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{
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}
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static void mainboard_enable(device_t dev)
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{
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dev->ops->init = &mainboard_init;
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}
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struct chip_operations mainboard_ops = {
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.name = CONFIG_MAINBOARD_PART_NUMBER,
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.enable_dev = mainboard_enable,
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};
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#include <soc/memlayout.ld>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <reset.h>
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void hard_reset(void)
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{
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <arch/cache.h>
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#include <arch/cpu.h>
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#include <arch/exception.h>
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#include <arch/io.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <delay.h>
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#include <program_loading.h>
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#include <romstage_handoff.h>
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#include <symbols.h>
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void main(void)
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{
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console_init();
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exception_init();
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cbmem_initialize_empty();
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run_ramstage();
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}
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