a6dbfb5808
Most things still need to be filled in, but this will allow us to build boards which use this SOC. [pg: separated out from the combined commit that added both SoC and board. Added board_info.txt that will be added downstream, too.] Change-Id: I7facce7b98a5d19fb77746b1aee67fff74da8150 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840 Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332385 Reviewed-on: https://review.coreboot.org/14279 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
38 lines
1 KiB
Makefile
38 lines
1 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright 2016 Rockchip Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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bootblock-y += boardid.c
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bootblock-y += bootblock.c
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bootblock-y += chromeos.c
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bootblock-y += memlayout.ld
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bootblock-y += reset.c
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verstage-y += boardid.c
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verstage-y += chromeos.c
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verstage-y += memlayout.ld
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verstage-y += memlayout.ld
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verstage-y += reset.c
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romstage-y += boardid.c
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romstage-y += chromeos.c
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romstage-y += memlayout.ld
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romstage-y += reset.c
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romstage-y += romstage.c
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ramstage-y += boardid.c
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ramstage-y += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += memlayout.ld
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ramstage-y += reset.c
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