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soc/amd/common/block/cpu: Remove magic number in memlayout 

The SPI DMA controller can only perform transactions on a cache line
boundary. This change removes the magic number and uses the #define to
make it clear.

BUG=b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Raul E Rangel 2021-07-23 14:53:05 -06:00 committed by Felix Held
parent fbf874fb38
commit a76e647094
1 changed files with 2 additions and 2 deletions
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4
src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
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@ -103,8 +103,8 @@ SECTIONS
* the payload on non-S3 boots, so we don't need to reserve it from the * the payload on non-S3 boots, so we don't need to reserve it from the
* OS. The 64 byte alignment is required by the SPI DMA controller. * OS. The 64 byte alignment is required by the SPI DMA controller.
*/ */
. = ALIGN(64); . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, 64) REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, ARCH_CACHELINE_ALIGN_SIZE)
#endif #endif
RAMSTAGE(CONFIG_RAMBASE, 8M) RAMSTAGE(CONFIG_RAMBASE, 8M)