soc/intel/*/smihandler: Only compile in TCO SMI handler if needed

commit 7f9ceef disables TCO SMIs unless specifically enabled, so help
the linker throw out the function that handles them in that case.

Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Michael Niewöhner

src/soc/intel/apollolake/smihandler.c

@@ -39,7 +39,9 @@ const smi_handler_t southbridge_smi[32] = {
 	[APM_STS_BIT] = smihandler_southbridge_apmc,
 	[PM1_STS_BIT] = smihandler_southbridge_pm1,
 	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
 	[TCO_STS_BIT] = smihandler_southbridge_tco,
+#endif
 	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
 #if CONFIG(SOC_ESPI)
 	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,

src/soc/intel/cannonlake/smihandler.c

@@ -48,7 +48,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
 	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
 	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
 	[MCSMI_STS_BIT] = smihandler_southbridge_mc,
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
 	[TCO_STS_BIT] = smihandler_southbridge_tco,
+#endif
 	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
 	[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
 };

src/soc/intel/icelake/smihandler.c

@@ -46,7 +46,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
 	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
 	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
 	[MCSMI_STS_BIT] = smihandler_southbridge_mc,
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
 	[TCO_STS_BIT] = smihandler_southbridge_tco,
+#endif
 	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
 	[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
 };

src/soc/intel/skylake/smihandler.c

@@ -26,7 +26,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
 	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
 	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
 	[MCSMI_STS_BIT] = smihandler_southbridge_mc,
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
 	[TCO_STS_BIT] = smihandler_southbridge_tco,
+#endif
 	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
 	[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
 };

src/soc/intel/tigerlake/smihandler.c

@@ -46,7 +46,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
 	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
 	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
 	[MCSMI_STS_BIT] = smihandler_southbridge_mc,
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
 	[TCO_STS_BIT] = smihandler_southbridge_tco,
+#endif
 	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
 	[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
 };