superio/ite: allow 24 MHz clock for external sensor interface

The interface selection register of the environment controller (EC)
gives the choice between "Internal generated 32 MHz" and "24 MHz" for
the "SST/PECI Host Controller Clock Selection".

Previously the chip was always configured for the 32 MHz clock. Add an
option that can be set from devicetree.cb to allow using the 24 MHz
clock.

Without this setting the automatic fan control on an Acer Aspire M3800
was slow to respond to temperature changes.

Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44166
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Büchler 2020-08-02 15:38:10 +02:00 committed by Felix Held
parent e693b1d549
commit a815272b7b
2 changed files with 12 additions and 0 deletions

View File

@ -264,6 +264,13 @@ void ite_ec_init(const u16 base, const struct ite_ec_config *const conf)
ITE_EC_INTERFACE_SMB_ENABLE); ITE_EC_INTERFACE_SMB_ENABLE);
} }
/* Set SST/PECI Host Controller Clock to either 24 MHz or internal 32 MHz */
if (conf->smbus_24mhz) {
pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT,
pnp_read_hwm5_index(base, ITE_EC_INTERFACE_SELECT) |
ITE_EC_INTERFACE_CLOCK_24MHZ);
}
/* Enable reading of voltage pins */ /* Enable reading of voltage pins */
pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask);

View File

@ -91,6 +91,11 @@ struct ite_ec_config {
* Enable SMBus for external thermal sensor. * Enable SMBus for external thermal sensor.
*/ */
bool smbus_en; bool smbus_en;
/*
* Select 24 MHz clock for external host instead of an
* internally generated 32 MHz clock.
*/
bool smbus_24mhz;
}; };
/* Some shorthands for device trees */ /* Some shorthands for device trees */