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sb/intel/bd8x62x,i82801gx: Fix PCI bridge subsystem IDs 

Implementation of ich_pci_dev_enable_resources() used to have
a custom implementation to program PCI subsystem IDs for the
(legacy) PCI bus bridge.

With the local implementation removed, we no longer need the
custom .enable_resources callback.

Change-Id: I6f73fd0e4d5a1829d1555455c9a143f1d18a6116
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Petr Cvek <petrcvekcz@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-09-23 10:01:16 +03:00
parent a0b366d550
commit a84a7340b6
2 changed files with 2 additions and 58 deletions
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30
src/southbridge/intel/bd82x6x/pci.c
View File

@ -57,34 +57,6 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, SECSTS, reg16);
}
static void ich_pci_dev_enable_resources(struct device *dev)
{
uint16_t command;
command = pci_read_config16(dev, PCI_COMMAND);
command |= dev->command;
printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
}
static void ich_pci_bus_enable_resources(struct device *dev)
{
uint16_t ctrl;
/* enable IO in command register if there is VGA card
* connected with (even it does not claim IO resource)
*/
if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
dev->command |= PCI_COMMAND_IO;
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= dev->link_list->bridge_ctrl;
ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */
printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
/* This is the reason we need our own pci_bus_enable_resources */
ich_pci_dev_enable_resources(dev);
}
static struct pci_operations pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
@ -92,7 +64,7 @@ static struct pci_operations pci_ops = {
static struct device_operations device_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = ich_pci_bus_enable_resources,
.enable_resources = pci_bus_enable_resources,
.init = pci_init,
.scan_bus = pci_scan_bridge,
.ops_pci = &pci_ops,

30
src/southbridge/intel/i82801gx/pci.c
View File

@ -56,34 +56,6 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, SECSTS, reg16);
}
static void ich_pci_dev_enable_resources(struct device *dev)
{
uint16_t command;
command = pci_read_config16(dev, PCI_COMMAND);
command |= dev->command;
printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
pci_write_config16(dev, PCI_COMMAND, command);
}
static void ich_pci_bus_enable_resources(struct device *dev)
{
uint16_t ctrl;
/* enable IO in command register if there is VGA card
* connected with (even it does not claim IO resource)
*/
if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
dev->command |= PCI_COMMAND_IO;
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= dev->link_list->bridge_ctrl;
ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */
printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
/* This is the reason we need our own pci_bus_enable_resources */
ich_pci_dev_enable_resources(dev);
}
static struct pci_operations pci_ops = {
.set_subsystem = pci_dev_set_subsystem,
};
@ -91,7 +63,7 @@ static struct pci_operations pci_ops = {
static struct device_operations device_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = ich_pci_bus_enable_resources,
.enable_resources = pci_bus_enable_resources,
.init = pci_init,
.scan_bus = pci_scan_bridge,
.ops_pci = &pci_ops,