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google/kahlee: Add EC and GNVS ACPI 

Add ACPI support for the Google EC, which requires GNVS support
for passing information from the EC to firmware and OS.

Change-Id: I0a308bcd608a135cc9633273a05527f020b60743
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marc Jones 2017-06-18 17:35:27 -06:00 committed by Martin Roth
parent 257db58bdb
commit a8754bd2a3
3 changed files with 26 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/mainboard/google/kahlee/dsdt.asl
View File

@ -13,6 +13,8 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include "ec.h"
/* DefinitionBlock Statement */ /* DefinitionBlock Statement */
DefinitionBlock ( DefinitionBlock (
"DSDT.AML", /* Output filename */ "DSDT.AML", /* Output filename */
@ -25,6 +27,9 @@ DefinitionBlock (
{ /* Start of ASL file */ { /* Start of ASL file */
/* #include <arch/x86/acpi/debug.asl> */ /* as needed */ /* #include <arch/x86/acpi/debug.asl> */ /* as needed */
/* global NVS and variables */
#include <globalnvs.asl>
/* Globals for the platform */ /* Globals for the platform */
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
@ -74,6 +79,18 @@ DefinitionBlock (
} /* End \_SB scope */ } /* End \_SB scope */
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
/* Describe SMBUS for the Southbridge */ /* Describe SMBUS for the Southbridge */
#include <smbus.asl> #include <smbus.asl>

1
src/mainboard/google/kahlee/ec.c
View File

@ -15,6 +15,7 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include "ec.h" #include "ec.h"
#include <rules.h> #include <rules.h>
#include <soc/hudson.h> #include <soc/hudson.h>

9
src/mainboard/google/kahlee/ec.h
View File

@ -17,7 +17,6 @@
#define MAINBOARD_EC_H #define MAINBOARD_EC_H
#include <ec/ec.h> #include <ec/ec.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h> #include <ec/google/chromeec/ec_commands.h>
/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */ /* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */
@ -59,4 +58,12 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
/* Enable LID switch */
#define EC_ENABLE_LID_SWITCH
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
#define SIO_EC_ENABLE_COM1 /* Enable Serial Port 1 */
#endif #endif