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Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming. 

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao 2009-06-03 03:15:05 +00:00 committed by Zheng Bao
parent f8318fe8f9
commit a922b3195b
1 changed files with 1 additions and 1 deletions
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2
src/southbridge/amd/rs690/rs690_pcie.c
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@ -148,7 +148,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
/* waits until SB has trained to L0, poll for bit0-5 = 0x10 */
do {
reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0);
reg &= 0x1f; /* remain LSB 5 bits */
reg &= 0x3f; /* remain LSB [5:0] bits */
} while (LC_STATE_RECONFIG_GPPSB != reg);
/* ensures that virtual channel negotiation is completed. poll for bit1 = 0 */