a922b3195b
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
391 lines
12 KiB
C
391 lines
12 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <delay.h>
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#include "rs690.h"
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/*------------------------------------------------
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* Global variable
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------------------------------------------------*/
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PCIE_CFG AtiPcieCfg = {
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PCIE_ENABLE_STATIC_DEV_REMAP, /* Config */
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0, /* ResetReleaseDelay */
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0, /* Gfx0Width */
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0, /* Gfx1Width */
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0, /* GfxPayload */
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0, /* GppPayload */
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0, /* PortDetect, filled by GppSbInit */
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0, /* PortHp */
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0, /* DbgConfig */
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0, /* DbgConfig2 */
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0, /* GfxLx */
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0, /* GppLx */
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0, /* NBSBLx */
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0, /* PortSlotInit */
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0, /* Gfx0Pwr */
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0, /* Gfx1Pwr */
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0 /* GppPwr */
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};
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static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port);
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static void ValidatePortEn(device_t nb_dev);
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static void ValidatePortEn(device_t nb_dev)
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{
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}
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/*****************************************************************
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* Compliant with CIM_33's PCIEPowerOffGppPorts
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* Power off unused GPP lines
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*****************************************************************/
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static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
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{
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u32 reg;
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u16 state_save;
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struct southbridge_amd_rs690_config *cfg =
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(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
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u8 state = cfg->port_enable;
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if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS))
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state &= AtiPcieCfg.PortDetect;
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state = ~state;
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state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
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state_save = state << 17;
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state &= !(AtiPcieCfg.PortHp);
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reg = nbmisc_read_index(nb_dev, 0x0c);
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reg |= state;
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nbmisc_write_index(nb_dev, 0x0c, reg);
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reg = nbmisc_read_index(nb_dev, 0x08);
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reg |= state_save;
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nbmisc_write_index(nb_dev, 0x08, reg);
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if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES)
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&& !(AtiPcieCfg.
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Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
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PCIE_GFX_COMPLIANCE))) {
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}
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/* step 3 Power Down Control for Southbridge */
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reg = nbpcie_p_read_index(dev, 0xa2);
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switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */
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case 1:
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nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
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break;
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case 2:
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nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
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break;
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default:
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break;
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}
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}
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static void pcie_init(struct device *dev)
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{
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/* Enable pci error detecting */
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u32 dword;
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printk_debug("pcie_init in rs690_pcie.c\n");
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/* System error enable */
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dword = pci_read_config32(dev, 0x04);
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dword |= (1 << 8); /* System error enable */
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dword |= (1 << 30); /* Clear possible errors */
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pci_write_config32(dev, 0x04, dword);
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}
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/**********************************************************************
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**********************************************************************/
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static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
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{
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u32 reg;
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struct southbridge_amd_rs690_config *cfg =
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(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
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/* enables GPP reconfiguration */
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reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
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reg |=
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(RECONFIG_GPPSB_EN + RECONFIG_GPPSB_LINK_CONFIG +
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RECONFIG_GPPSB_ATOMIC_RESET);
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nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
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/* sets desired GPPSB configurations, bit4-7 */
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reg = nbmisc_read_index(nb_dev, 0x67);
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reg &= 0xffffff0f; /* clean */
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reg |= cfg->gpp_configuration << 4;
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nbmisc_write_index(nb_dev, 0x67, reg);
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/* read bit14 and write back its inverst value */
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reg = nbmisc_read_index(nb_dev, PCIE_NBCFG_REG7);
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reg ^= RECONFIG_GPPSB_GPPSB;
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nbmisc_write_index(nb_dev, PCIE_NBCFG_REG7, reg);
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/* delay 1ms */
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mdelay(1);
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/* waits until SB has trained to L0, poll for bit0-5 = 0x10 */
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do {
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reg = nbpcie_p_read_index(sb_dev, PCIE_LC_STATE0);
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reg &= 0x3f; /* remain LSB [5:0] bits */
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} while (LC_STATE_RECONFIG_GPPSB != reg);
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/* ensures that virtual channel negotiation is completed. poll for bit1 = 0 */
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do {
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reg =
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pci_ext_read_config32(nb_dev, sb_dev,
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PCIE_VC0_RESOURCE_STATUS);
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} while (reg & VC_NEGOTIATION_PENDING);
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}
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/*****************************************************************
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* The rs690 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
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* Space to a 256MB range within the first 4GB of addressable memory.
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*****************************************************************/
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void enable_pcie_bar3(device_t nb_dev)
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{
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printk_debug("enable_pcie_bar3()\n");
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set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
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set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
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pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */
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pci_write_config32(nb_dev, 0x20, 0x00000000);
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set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */
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ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
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}
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/*****************************************************************
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* We should disable bar3 when we want to exit rs690_enable, because bar3 will be
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* remapped in set_resource later.
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*****************************************************************/
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void disable_pcie_bar3(device_t nb_dev)
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{
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printk_debug("disable_pcie_bar3()\n");
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set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */
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pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */
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ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
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}
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/*****************************************
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* Compliant with CIM_33's PCIEGPPInit
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* nb_dev:
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* root bridge struct
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* dev:
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* p2p bridge struct
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* port:
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* p2p bridge number, 4-8
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*****************************************/
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void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
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{
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u8 reg8;
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u16 reg16;
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device_t sb_dev;
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struct southbridge_amd_rs690_config *cfg =
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(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
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printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
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/* init GPP core */
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set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8,
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1 << 8);
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/* PCIE initialization 5.10.2: rpr 2.12*/
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set_pcie_enable_bits(nb_dev, 0x02 | PCIE_CORE_INDEX_GPPSB, 1 << 0, 1 << 0); /* no description in datasheet. */
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/* init GPPSB port */
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/* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 0*/
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set_pcie_enable_bits(dev, 0x70, 7 << 16, 0xd << 16);
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/* PCIE initialization 5.10.2: rpr 2.4 */
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set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 14);
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/* Do not gate the electrical idle from the PHY and enables the escape from L1L23 */
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set_pcie_enable_bits(dev, 0xA0, ~0xffffffbf, (3 << 30) | (3 << 12) | (3 << 4));
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/* PCIE initialization 5.10.2: rpr 2.13 */
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set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 6);
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/* SLOT_IMPLEMENTED in pcieConfig space */
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reg8 = pci_read_config8(dev, 0x5b);
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reg8 |= 1 << 0;
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pci_write_config8(dev, 0x5b, reg8);
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reg16 = pci_read_config16(dev, 0x5a);
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reg16 |= 0x100;
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pci_write_config16(dev, 0x5a, reg16);
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nbmisc_write_index(nb_dev, 0x34, 0);
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/* check compliance rpr step 2.1*/
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if (AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE) {
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u32 tmp;
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tmp = nbmisc_read_index(nb_dev, 0x67);
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tmp |= 1 << 3;
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nbmisc_write_index(nb_dev, 0x67, tmp);
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}
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/* step 5: dynamic slave CPL buffer allocation */
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set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11);
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/* step 5a: Training for GPP devices */
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/* init GPP */
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switch (port) {
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case 4: /* GPP */
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case 5:
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case 6:
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case 7:
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/* Blocks DMA traffic during C3 state */
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set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
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/* Enabels TLP flushing */
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set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
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/* check port enable */
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if (cfg->port_enable & (1 << port)) {
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PcieReleasePortTraining(nb_dev, dev, port);
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if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
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u8 res = PcieTrainPort(nb_dev, dev, port);
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printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res);
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if (res) {
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AtiPcieCfg.PortDetect |= 1 << port;
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}
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}
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}
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break;
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case 8: /* SB */
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break;
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}
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PciePowerOffGppPorts(nb_dev, dev, port);
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/* step 5b: GFX devices in a GPP slot */
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/* step 6a: VCI */
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sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
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if (port == 8) {
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/* Clear bits 7:1 */
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pci_ext_write_config32(nb_dev, sb_dev, 0x114, 0x3f << 1, 0 << 1);
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/* Maps Traffic Class 1-7 to VC1 */
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pci_ext_write_config32(nb_dev, sb_dev, 0x120, 0x7f << 1, 0x7f << 1);
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/* Assigns VC ID to 1 */
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pci_ext_write_config32(nb_dev, sb_dev, 0x120, 7 << 24, 1 << 24);
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/* Enables VC1 */
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pci_ext_write_config32(nb_dev, sb_dev, 0x120, 1 << 31, 1 << 31);
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#if 0
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do {
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reg16 = pci_ext_read_config32(nb_dev, sb_dev, 0x124);
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reg16 &= 0x2;
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} while (reg16); /*bit[1] = 0 means VC1 flow control initialization is successful */
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#endif
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}
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/* step 6b: L0s for the southbridge link */
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/* To enalbe L0s in the southbridage*/
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/* step 6c: L0s for the GPP link(s) */
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/* To eable L0s in the RS690 for the GPP port(s) */
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set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
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set_pcie_enable_bits(dev, 0xa0, 0xf << 8, 0x9 << 8);
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reg16 = pci_read_config16(dev, 0x68);
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reg16 |= 1 << 0;
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pci_write_config16(dev, 0x68, reg16);
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/* step 6d: ASPM L1 for the southbridge link */
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/* To enalbe L1s in the southbridage*/
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/* step 6e: ASPM L1 for GPP link(s) */;
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set_pcie_enable_bits(nb_dev, 0xf9, 3 << 13, 2 << 13);
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set_pcie_enable_bits(dev, 0xa0, 3 << 12, 3 << 12);
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set_pcie_enable_bits(dev, 0xa0, 0xf << 4, 3 << 4);
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reg16 = pci_read_config16(dev, 0x68);
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reg16 &= ~0xff;
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reg16 |= 1 << 1;
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pci_write_config16(dev, 0x68, reg16);
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/* step 6f: Turning off PLL during L1/L23 */
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set_pcie_enable_bits(nb_dev, 0x40, 1 << 3, 1 << 3);
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set_pcie_enable_bits(nb_dev, 0x40, 1 << 9, 1 << 9);
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/* step 6g: TXCLK clock gating */
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set_nbmisc_enable_bits(nb_dev, 0x7, 3 << 4, 3 << 4);
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set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 22, 1 << 22);
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set_pcie_enable_bits(nb_dev, 0x11, 0xf << 4, 0xc << 4);
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/* step 6h: LCLK clock gating, done in rs690_config_misc_clk() */
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}
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/*****************************************
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* Compliant with CIM_33's PCIEConfigureGPPCore
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*****************************************/
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void config_gpp_core(device_t nb_dev, device_t sb_dev)
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{
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u32 reg;
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struct southbridge_amd_rs690_config *cfg =
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(struct southbridge_amd_rs690_config *)nb_dev->chip_info;
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reg = nbmisc_read_index(nb_dev, 0x20);
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if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
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reg &= 0xfffffffd; /* set bit1 = 0 */
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else
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reg |= 0x2; /* set bit1 = 1 */
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nbmisc_write_index(nb_dev, 0x20, reg);
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reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG_GPPSB at bit 4-7 */
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if (cfg->gpp_configuration != ((reg >> 4) & 0xf))
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switching_gpp_configurations(nb_dev, sb_dev);
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ValidatePortEn(nb_dev);
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}
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/*****************************************
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* Compliant with CIM_33's PCIEMiscClkProg
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*****************************************/
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void pcie_config_misc_clk(device_t nb_dev)
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{
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u32 reg;
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struct bus pbus; /* fake bus for dev0 fun1 */
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reg = pci_read_config32(nb_dev, 0x4c);
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reg |= 1 << 0;
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pci_write_config32(nb_dev, 0x4c, reg);
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if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
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/* TXCLK Clock Gating */
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set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0);
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set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
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set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
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/* LCLK Clock Gating */
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reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
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reg &= ~(1 << 16);
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pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
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}
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if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
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/* TXCLK Clock Gating */
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set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4);
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set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
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set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GPPSB, (3 << 6) | (~0xf), 3 << 6);
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/* LCLK Clock Gating */
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reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94);
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reg &= ~(1 << 24);
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pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg);
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}
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reg = pci_read_config32(nb_dev, 0x4c);
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reg &= ~(1 << 0);
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pci_write_config32(nb_dev, 0x4c, reg);
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}
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