Zheng Bao a922b3195b Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming. ... Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2009-06-03 03:15:05 +00:00
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chip.h	Add AMD rs690 VID DID reporting and some minor cleanups.	2008-12-01 19:49:57 +00:00
Config.lb
rs690.c	I just went on a bugfix frenzy and fixed all printk format warnings	2009-03-04 01:06:41 +00:00
rs690.h	Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.	2008-10-13 21:41:24 +00:00
rs690_cmn.c	coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3	2009-02-28 20:10:20 +00:00
rs690_early_setup.c	Handle RS690 quirks for 1 GHz noncoherent HyperTransport.	2008-12-23 17:20:46 +00:00
rs690_gfx.c	I just went on a bugfix frenzy and fixed all printk format warnings	2009-03-04 01:06:41 +00:00
rs690_ht.c	Add AMD rs690 VID DID reporting and some minor cleanups.	2008-12-01 19:49:57 +00:00
rs690_pcie.c	Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming.	2009-06-03 03:15:05 +00:00