GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

acpi: Move ECAM resource below PNP0C02 device in a common place 

From the Linux documentation (Documentation/PCI/acpi-info.rst):
[6] PCI Firmware 3.2, sec 4.1.2:
    If the operating system does not natively comprehend reserving the
    MMCFG region, the MMCFG region must be reserved by firmware.  The
    address range reported in the MCFG table or by _CBA method (see Section
    4.1.3) must be reserved by declaring a motherboard resource.  For most
    systems, the motherboard resource would appear at the root of the ACPI
    namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
    the resources in this case should not be claimed in the root PCI bus’s
    _CRS.  The resources can optionally be returned in Int15 E820 or
    EFIGetMemoryMap as reserved memory but must always be reported through
    ACPI as a motherboard resource.

So in order for the OS to use ECAM MMCONF over legacy PCI IO
configuration, a PNP0C02 HID device needs to reserve this region.

As no AMD platform has this defined in DSDT this fixes Linux using
legacy PCI IO configuration over MMCONF. Tianocore messes with e820
table in such a way that it prevents Linux from using PCIe ECAM. This
change fixes that problem.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2023-06-08 15:22:27 +02:00 committed by Lean Sheng Tan
parent d31cbc74d1
commit a9a92ac961
14 changed files with 23 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/acpi/dsdt_top.asl
View File

@ -40,5 +40,28 @@ Scope(\_SB) {
/* PCIe Configuration Space */ /* PCIe Configuration Space */
OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
/* From the Linux documentation (Documentation/PCI/acpi-info.rst):
* [6] PCI Firmware 3.2, sec 4.1.2:
* If the operating system does not natively comprehend reserving the
* MMCFG region, the MMCFG region must be reserved by firmware. The
* address range reported in the MCFG table or by _CBA method (see Section
* 4.1.3) must be reserved by declaring a motherboard resource. For most
* systems, the motherboard resource would appear at the root of the ACPI
* namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
* the resources in this case should not be claimed in the root PCI bus's
* _CRS. The resources can optionally be returned in Int15 E820 or
* EFIGetMemoryMap as reserved memory but must always be reported through
* ACPI as a motherboard resource.
*/
Device (PERC) // PCI ECAM Resource Consumption
{
Name (_HID, EisaId("PNP0C02"))
Name (_CRS, ResourceTemplate()
{
Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS,
CONFIG_ECAM_MMCONF_LENGTH)
})
}
} }
#endif #endif

1
src/northbridge/intel/gm45/acpi/gm45.asl
View File

@ -16,7 +16,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

1
src/northbridge/intel/haswell/acpi/hostbridge.asl
View File

@ -178,7 +178,6 @@ Device (PDRC)
Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM
Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

2
src/northbridge/intel/i945/acpi/i945.asl
View File

@ -31,7 +31,6 @@ Device (PDRC)
// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
// Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
// Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
//}) //})
@ -40,7 +39,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

1
src/northbridge/intel/ironlake/acpi/ironlake.asl
View File

@ -14,7 +14,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

1
src/northbridge/intel/pineview/acpi/pineview.asl
View File

@ -15,7 +15,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */

7
src/northbridge/intel/sandybridge/acpi/sandybridge.asl
View File

@ -15,7 +15,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB)
Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB)
Memory32Fixed(ReadWrite, 0, 0x00001000, EGPB) Memory32Fixed(ReadWrite, 0, 0x00001000, EGPB)
Memory32Fixed(ReadWrite, 0, 0x04000000, PCIX)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
@ -37,12 +36,6 @@ Device (PDRC)
CreateDwordField (PDRS, ^EGPB._BAS, EBR0) CreateDwordField (PDRS, ^EGPB._BAS, EBR0)
EBR0 = \_SB.PCI0.MCHC.EPBR << 12 EBR0 = \_SB.PCI0.MCHC.EPBR << 12
CreateDwordField (PDRS, ^PCIX._BAS, XBR0)
XBR0 = \_SB.PCI0.MCHC.PXBR << 26
CreateDwordField (PDRS, ^PCIX._LEN, XSZ0)
XSZ0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ
Return(PDRS) Return(PDRS)
} }
} }

1
src/northbridge/intel/x4x/acpi/x4x.asl
View File

@ -13,7 +13,6 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

5
src/soc/intel/apollolake/acpi/northbridge.asl
View File

@ -116,11 +116,6 @@ Device (PDRC) /* PCI Device Resource Consumption */
{ {
Name (BUF0, ResourceTemplate () Name (BUF0, ResourceTemplate ()
{ {
/* PCI Express BAR */
Memory32Fixed (ReadWrite,
CONFIG_ECAM_MMCONF_BASE_ADDRESS,
CONFIG_ECAM_MMCONF_LENGTH, PCIX)
/* Local APIC range (0xfee0_0000 to 0xfeef_ffff) */ /* Local APIC range (0xfee0_0000 to 0xfeef_ffff) */
Memory32Fixed (ReadOnly, 0x0fee00000, 0x00010000, LIOH) Memory32Fixed (ReadOnly, 0x0fee00000, 0x00010000, LIOH)
}) })

1
src/soc/intel/baytrail/acpi/southcluster.asl
View File

@ -189,7 +189,6 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)

1
src/soc/intel/braswell/acpi/southcluster.asl
View File

@ -188,7 +188,6 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)

11
src/soc/intel/common/block/acpi/acpi/northbridge.asl
View File

@ -269,11 +269,6 @@ Device (PDRC)
*/ */
Memory32Fixed (ReadWrite, 0, EP_BASE_SIZE, EGPB) Memory32Fixed (ReadWrite, 0, EP_BASE_SIZE, EGPB)
/* PCI Express BAR _BAS and _LEN will be updated in
* _CRS below according to B0:D0:F0:Reg.60h
*/
Memory32Fixed (ReadWrite, 0, 0, PCIX)
/* VTD engine memory range. */ /* VTD engine memory range. */
Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
@ -301,12 +296,6 @@ Device (PDRC)
CreateDwordField (BUF0, EGPB._BAS, EBR0) CreateDwordField (BUF0, EGPB._BAS, EBR0)
EBR0 = \_SB.PCI0.GEPB () EBR0 = \_SB.PCI0.GEPB ()
CreateDwordField (BUF0, PCIX._BAS, XBR0)
XBR0 = \_SB.PCI0.GPCB ()
CreateDwordField (BUF0, PCIX._LEN, XSZ0)
XSZ0 = \_SB.PCI0.GPCL ()
CreateDwordField (BUF0, FIOH._BAS, FBR0) CreateDwordField (BUF0, FIOH._BAS, FBR0)
FBR0 = 0x100000000 - CONFIG_ROM_SIZE FBR0 = 0x100000000 - CONFIG_ROM_SIZE

2
src/soc/intel/denverton_ns/acpi/northcluster.asl
View File

@ -121,8 +121,6 @@ Device (PDRC)
Name (_UID, 1) Name (_UID, 1)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
// PCIEXBAR memory range
Memory32Fixed(ReadOnly, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
// TSEG // TSEG
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB) Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB)
}) })

11
src/soc/intel/skylake/acpi/systemagent.asl
View File

@ -287,11 +287,6 @@ Device (PDRC)
*/ */
Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
/* PCI Express BAR _BAS and _LEN will be updated in
* _CRS below according to B0:D0:F0:Reg.60h
*/
Memory32Fixed (ReadWrite, 0, 0, PCIX)
/* VTD engine memory range. */ /* VTD engine memory range. */
Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
@ -314,12 +309,6 @@ Device (PDRC)
CreateDwordField (BUF0, EGPB._BAS, EBR0) CreateDwordField (BUF0, EGPB._BAS, EBR0)
EBR0 = \_SB.PCI0.GEPB () EBR0 = \_SB.PCI0.GEPB ()
CreateDwordField (BUF0, PCIX._BAS, XBR0)
XBR0 = \_SB.PCI0.GPCB ()
CreateDwordField (BUF0, PCIX._LEN, XSZ0)
XSZ0 = \_SB.PCI0.GPCL ()
CreateDwordField (BUF0, FIOH._BAS, FBR0) CreateDwordField (BUF0, FIOH._BAS, FBR0)
FBR0 = 0x100000000 - CONFIG_ROM_SIZE FBR0 = 0x100000000 - CONFIG_ROM_SIZE