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rk3399: add GPIO register definitions for SDMMC0 

The code needs to be able to set drive strength for the pins used for
SDMMC0 interface. This patch adds the definitions for the two
registers, as per page 378 of the RK3399 TRM Part 1.

Instead of calculation of the reserved range size just use known
offsets of the registers included in the structure.

BRANCH=none
BUG=chrome-os-partner:53257
TEST=with the upcoming driver change it is possible to boot chrome OS
     on Gru from various micro SD cards which were failing before.

Change-Id: I63bf37432ec7f3bdf7e9c6a79d51c31de122dae9
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: c6d6dc5e5e6cc81c173603d4eb21ae803a47815d
Original-Change-Id: Ibe7584e77b446435ab1264dcf8fc8bfe0c50438e
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/344490
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14852
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This commit is contained in:
Vadim Bendebury 2016-05-12 16:40:37 +08:00 committed by Martin Roth
parent 2832c4125b
commit a9cd4a2f11
1 changed files with 4 additions and 1 deletions
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5
src/soc/rockchip/rk3399/include/soc/grf.h
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@ -149,7 +149,10 @@ struct rk3399_grf_regs {
u32 gpio2_sr[3][4];
u32 reserved23[4];
u32 gpio2_smt[3][4];
u32 reserved24[0x44];
u32 reserved24[(0xe130 - 0xe0ec)/4 - 1];
u32 gpio4b_e01;
u32 gpio4b_e2;
u32 reserved24a[(0xe200 - 0xe134)/4 - 1];
u32 soc_con0;
u32 soc_con1;
u32 soc_con2;