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nb/intel/sandybridge: sort LANEBASE_* defines by their address 

Change-Id: I32fcd36298f41d3b6d8b3e16b6641b9404220461
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Felix Held 2020-01-15 14:40:14 +01:00
parent fb19c8aae0
commit aa30d6237e
1 changed files with 1 additions and 1 deletions
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src/northbridge/intel/sandybridge/sandybridge.h
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@ -139,11 +139,11 @@ enum platform_type {
#define LANEBASE_B1 0x0200
#define LANEBASE_B2 0x0400
#define LANEBASE_B3 0x0600
#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */
#define LANEBASE_B4 0x1000
#define LANEBASE_B5 0x1200
#define LANEBASE_B6 0x1400
#define LANEBASE_B7 0x1600
#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */
/* byte lane register offsets */
#define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */