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mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1 

Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec.

BUG=none
BRANCH=firmware-brya-14505.B
TEST=Insert a SD card or NIC AIC on PCIe slot1 and run
'suspend_stress_test -c 1'. The RP8 should not cause suspend issue.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72422
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Cliff Huang 2023-01-24 17:14:46 -08:00 committed by Felix Held
parent 0539962835
commit aa5e362537
2 changed files with 4 additions and 4 deletions
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4
src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
View File

@ -95,9 +95,9 @@ chip soc/intel/alderlake
}" }"
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
register "enable_delay_ms" = "50" register "enable_delay_ms" = "100"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
register "reset_off_delay_ms" = "20" register "reset_delay_ms" = "20"
register "srcclk_pin" = "7" register "srcclk_pin" = "7"
device generic 0 on device generic 0 on
end end

4
src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
View File

@ -95,9 +95,9 @@ chip soc/intel/alderlake
}" }"
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
register "enable_delay_ms" = "50" register "enable_delay_ms" = "100"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
register "reset_off_delay_ms" = "20" register "reset_delay_ms" = "20"
register "srcclk_pin" = "7" register "srcclk_pin" = "7"
device generic 0 on device generic 0 on
end end