elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE

The wake source macro for GPE events was using 'GPIO'. However,
current usage is really all GPEs. Therefore, provide clarity
in the naming in order to allow for proper GPIO wake events
that are separate from the ACPI GPE block.

BUG=b:159947207

Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/include/elog.h

@@ -79,7 +79,7 @@
 #define  ELOG_WAKE_SOURCE_PME              0x01
 #define  ELOG_WAKE_SOURCE_PME_INTERNAL     0x02
 #define  ELOG_WAKE_SOURCE_RTC              0x03
-#define  ELOG_WAKE_SOURCE_GPIO             0x04
+#define  ELOG_WAKE_SOURCE_GPE              0x04
 #define  ELOG_WAKE_SOURCE_SMBUS            0x05
 #define  ELOG_WAKE_SOURCE_PWRBTN           0x06
 #define  ELOG_WAKE_SOURCE_PME_HDA          0x07

src/soc/amd/common/block/acpi/acpi.c

@@ -90,7 +90,7 @@ static void log_gpe_events(const struct acpi_pm_gpe_state *state)
 
 	for (i = 0; i <= 31; i++) {
 		if (valid_gpe & (1U << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i);
 	}
 }
 

src/soc/intel/apollolake/elog.c

@@ -18,7 +18,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 
 	for (i = 0; i <= 31; i++) {
 		if (gpe0_sts & (1 << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
 	}
 }
 

src/soc/intel/baytrail/elog.c

@@ -68,7 +68,7 @@ static void log_wake_events(const struct chipset_power_state *ps)
 	i = 0;
 	while (gpio_mask) {
 		if (gpio_mask & gpe0_sts)
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i);
 		gpio_mask <<= 1;
 		i++;
 	}

src/soc/intel/braswell/elog.c

@@ -68,7 +68,7 @@ static void log_wake_events(const struct chipset_power_state *ps)
 	i = 0;
 	while (gpio_mask) {
 		if (gpio_mask & gpe0_sts)
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i);
 		gpio_mask <<= 1;
 		i++;
 	}

src/soc/intel/broadwell/elog.c

@@ -16,7 +16,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 
 	for (i = 0; i <= 31; i++) {
 		if (gpe0_sts & (1 << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
 	}
 }
 
@@ -48,7 +48,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps)
 
 	/* GPIO27 */
 	if (ps->gpe0_sts[GPE_STD] & GP27_STS)
-		elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, 27);
+		elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, 27);
 
 	/* Log GPIO events in set 1-3 */
 	pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);

src/soc/intel/cannonlake/elog.c

@@ -97,7 +97,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 
 	for (i = 0; i <= 31; i++) {
 		if (gpe0_sts & (1 << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
 	}
 }
 

src/soc/intel/icelake/elog.c

@@ -16,7 +16,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 
 	for (i = 0; i <= 31; i++) {
 		if (gpe0_sts & (1 << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
 	}
 }
 

src/soc/intel/jasperlake/elog.c

@@ -16,7 +16,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 
 	for (i = 0; i <= 31; i++) {
 		if (gpe0_sts & (1 << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
 	}
 }
 

src/soc/intel/skylake/elog.c

@@ -22,7 +22,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 
 	for (i = 0; i <= 31; i++) {
 		if (gpe0_sts & (1 << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
 	}
 }
 

src/soc/intel/tigerlake/elog.c

@@ -16,7 +16,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 
 	for (i = 0; i <= 31; i++) {
 		if (gpe0_sts & (1 << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
 	}
 }
 

src/southbridge/intel/bd82x6x/elog.c

@@ -87,7 +87,7 @@ void pch_log_state(void)
 	/* GPIO 0-15 */
 	for (i = 0; i < 16; i++) {
 		if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i))))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i);
 	}
 
 	/* SMBUS Wake */

src/southbridge/intel/lynxpoint/elog.c

@@ -36,7 +36,7 @@ static void pch_log_gpio_gpe(u32 gpe0_sts_reg, u32 gpe0_en_reg, int start)
 
 	for (i = 0; i <= 31; i++) {
 		if (gpe0_sts & (1 << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
 	}
 }
 
@@ -64,7 +64,7 @@ static void pch_log_gpe(void)
 	gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en;
 	for (i = 0; i <= 15; i++) {
 		if (gpe0_sts & (1 << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i);
 	}
 
 	/*
@@ -78,7 +78,7 @@ static void pch_log_gpe(void)
 		if (!gpe0_high_gpios[i])
 			continue;
 		if (gpe0_sts & (1 << i))
-			elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO,
+			elog_add_event_wake(ELOG_WAKE_SOURCE_GPE,
 					    gpe0_high_gpios[i]);
 	}
 }