Redefine pci_bus_default_ops as function

Taking device_t as a parameter, this allows to alter the PCI config
access handlers. This is useful to add tracing of PCI config writes
for devices having problems to initialise correctly.

On older AMD platform PCI MMIO may not be able to fully configure all
PCI devices/nodes, while MMIO_SUPPORT_DEFAULT would be preferred due
to its atomic nature. So those can be forced to IO config instead.

Change-Id: I2162884185bbfe461b036caf737980b45a51e522
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3608
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki 2013-07-04 17:17:45 +03:00
parent 026ff3e436
commit aad0747216
5 changed files with 34 additions and 41 deletions

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@ -20,9 +20,6 @@
#ifndef ARCH_ARMV7_PCI_OPS_H
#define ARCH_ARMV7_PCI_OPS_H
static inline const struct pci_bus_operations *pci_config_default(void)
{
return NULL;
}
/* Empty stub until PCI includes are properly fixed. */
#endif

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@ -7,19 +7,6 @@ extern const struct pci_bus_operations pci_cf8_conf1;
extern const struct pci_bus_operations pci_ops_mmconf;
#endif
#if CONFIG_MMCONF_SUPPORT_DEFAULT
#define pci_bus_default_ops &pci_ops_mmconf
#else
#define pci_bus_default_ops &pci_cf8_conf1
#endif
static inline const struct pci_bus_operations *pci_config_default(void)
{
#if CONFIG_MMCONF_SUPPORT_DEFAULT
return &pci_ops_mmconf;
#else
return &pci_cf8_conf1;
#endif
}
const struct pci_bus_operations *pci_bus_default_ops(device_t dev);
#endif /* ARCH_I386_PCI_OPS_H */

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@ -25,9 +25,30 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
const struct pci_bus_operations *pci_bus_default_ops(device_t dev)
{
#if CONFIG_MMCONF_SUPPORT_DEFAULT
return &pci_ops_mmconf;
#else
return &pci_cf8_conf1;
#endif
}
static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, device_t dev)
{
const struct pci_bus_operations *bops;
bops = NULL;
if (bus && bus->dev && bus->dev->ops && bus->dev->ops->ops_pci_bus) {
bops = bus->dev->ops->ops_pci_bus(dev);
}
if (!bops)
bops = pci_bus_default_ops(dev);
return bops;
}
/*
* The only consumer of the return value of get_pbus() is ops_pci_bus().
* ops_pci_bus() can handle being passed NULL and auto-picks working ops.
* The only consumer of the return value of get_pbus() is pci_bus_ops().
* pci_bus_ops() can handle being passed NULL and auto-picks working ops.
*/
static struct bus *get_pbus(device_t dev)
{
@ -38,10 +59,10 @@ static struct bus *get_pbus(device_t dev)
else
pbus = dev->bus;
while (pbus && pbus->dev && !ops_pci_bus(pbus)) {
while (pbus && pbus->dev && !pci_bus_ops(pbus, dev)) {
if (pbus == pbus->dev->bus) {
printk(BIOS_ALERT, "%s in endless loop looking for a "
"parent bus with ops_pci_bus for %s, breaking "
"parent bus with pci_bus_ops for %s, breaking "
"out.\n", __func__, dev_path(dev));
break;
}
@ -64,42 +85,42 @@ static struct bus *get_pbus(device_t dev)
u8 pci_read_config8(device_t dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary,
return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}
u16 pci_read_config16(device_t dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary,
return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}
u32 pci_read_config32(device_t dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary,
return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}
void pci_write_config8(device_t dev, unsigned int where, u8 val)
{
struct bus *pbus = get_pbus(dev);
ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary,
pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary,
dev->path.pci.devfn, where, val);
}
void pci_write_config16(device_t dev, unsigned int where, u16 val)
{
struct bus *pbus = get_pbus(dev);
ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary,
pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary,
dev->path.pci.devfn, where, val);
}
void pci_write_config32(device_t dev, unsigned int where, u32 val)
{
struct bus *pbus = get_pbus(dev);
ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary,
pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary,
dev->path.pci.devfn, where, val);
}

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@ -42,7 +42,7 @@ struct device_operations {
#endif
const struct pci_operations *ops_pci;
const struct smbus_bus_operations *ops_smbus_bus;
const struct pci_bus_operations *ops_pci_bus;
const struct pci_bus_operations * (*ops_pci_bus)(device_t dev);
const struct pnp_mode_ops *ops_pnp_mode;
};
#endif

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@ -94,17 +94,5 @@ static inline const struct pci_operations *ops_pci(device_t dev)
return pops;
}
static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus)
{
const struct pci_bus_operations *bops;
bops = 0;
if (bus && bus->dev && bus->dev->ops) {
bops = bus->dev->ops->ops_pci_bus;
}
if (!bops)
bops = pci_config_default();
return bops;
}
#endif
#endif /* PCI_H */