soc/intel/denverton_ns: Rewrite pmutil using pmclib
Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25427 Reviewed-by: David Guckian Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Julien Viard de Galbert
Patrick Georgi
parent
c2540a958b
commit
ab1227226e
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@ -41,18 +41,6 @@ struct chipset_power_state {
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struct chipset_power_state *fill_power_state(void);
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/* Power Management Utility Functions. */
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uint32_t clear_smi_status(void);
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uint16_t clear_pm1_status(void);
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uint32_t clear_tco_status(void);
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uint32_t clear_gpe_status(void);
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void clear_pmc_status(void);
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void enable_smi(uint32_t mask);
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void disable_smi(uint32_t mask);
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void enable_pm1(uint16_t events);
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void enable_pm1_control(uint32_t mask);
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void disable_pm1_control(uint32_t mask);
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void enable_gpe(uint32_t mask);
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void disable_gpe(uint32_t mask);
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void disable_all_gpe(void);
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#endif /* _DENVERTON_NS_PM_H_ */
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@ -19,29 +19,12 @@
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#include <arch/io.h>
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#include <console/console.h>
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#include <intelblocks/pmclib.h>
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#include <soc/iomap.h>
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#include <soc/soc_util.h>
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#include <soc/pm.h>
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static void print_num_status_bits(int num_bits, uint32_t status,
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const char *const bit_names[])
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{
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int i;
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if (!status)
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return;
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for (i = num_bits - 1; i >= 0; i--) {
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if (status & (1 << i)) {
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if (bit_names[i])
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printk(BIOS_DEBUG, "%s ", bit_names[i]);
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else
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printk(BIOS_DEBUG, "BIT%d ", i);
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}
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}
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}
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static uint32_t print_smi_status(uint32_t smi_sts)
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const char *const *soc_smi_sts_array(size_t *a)
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{
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static const char *const smi_sts_bits[] = {
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[2] = "BIOS",
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@ -67,93 +50,11 @@ static uint32_t print_smi_status(uint32_t smi_sts)
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[31] = "LEGACY_USB3",
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};
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if (!smi_sts)
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return 0;
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printk(BIOS_DEBUG, "SMI_STS: ");
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print_num_status_bits(ARRAY_SIZE(smi_sts_bits), smi_sts, smi_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return smi_sts;
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*a = ARRAY_SIZE(smi_sts_bits);
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return smi_sts_bits;
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}
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static uint32_t reset_smi_status(void)
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{
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uint16_t pmbase = get_pmbase();
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uint32_t smi_sts = inl((uint16_t)(pmbase + SMI_STS));
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outl(smi_sts, (uint16_t)(pmbase + SMI_STS));
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return smi_sts;
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}
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uint32_t clear_smi_status(void) { return print_smi_status(reset_smi_status()); }
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void enable_smi(uint32_t mask)
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{
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uint16_t pmbase = get_pmbase();
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uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
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smi_en |= mask;
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outl(smi_en, (uint16_t)(pmbase + SMI_EN));
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}
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void disable_smi(uint32_t mask)
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{
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uint16_t pmbase = get_pmbase();
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uint32_t smi_en = inl((uint16_t)(pmbase + SMI_EN));
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smi_en &= ~mask;
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outl(smi_en, (uint16_t)(pmbase + SMI_EN));
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}
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void enable_pm1_control(uint32_t mask)
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{
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uint16_t pmbase = get_pmbase();
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uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
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pm1_cnt |= mask;
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outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
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}
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void disable_pm1_control(uint32_t mask)
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{
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uint16_t pmbase = get_pmbase();
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uint32_t pm1_cnt = inl((uint16_t)(pmbase + PM1_CNT));
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pm1_cnt &= ~mask;
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outl(pm1_cnt, (uint16_t)(pmbase + PM1_CNT));
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}
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static uint16_t reset_pm1_status(void)
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{
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uint16_t pmbase = get_pmbase();
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uint16_t pm1_sts = inw((uint16_t)(pmbase + PM1_STS));
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outw(pm1_sts, (uint16_t)(pmbase + PM1_STS));
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return pm1_sts;
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}
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static uint16_t print_pm1_status(uint16_t pm1_sts)
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{
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static const char *const pm1_sts_bits[] = {
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[0] = "TMROF", [4] = "BM", [5] = "GBL",
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[8] = "PWRBTN", [10] = "RTC", [11] = "PRBTNOR",
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[15] = "WAK",
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};
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if (!pm1_sts)
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return 0;
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printk(BIOS_SPEW, "PM1_STS: ");
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print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
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printk(BIOS_SPEW, "\n");
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return pm1_sts;
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}
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uint16_t clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); }
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void enable_pm1(uint16_t events)
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{
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uint16_t pmbase = get_pmbase();
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outw(events, (uint16_t)(pmbase + PM1_EN));
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}
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static uint32_t print_tco_status(uint32_t tco_sts)
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const char *const *soc_tco_sts_array(size_t *a)
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{
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static const char *const tco_sts_bits[] = {
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[0] = "NMI2SMI", [1] = "OS_TCO_SMI",
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@ -164,17 +65,11 @@ static uint32_t print_tco_status(uint32_t tco_sts)
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[17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI",
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};
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if (!tco_sts)
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return 0;
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printk(BIOS_DEBUG, "TCO_STS: ");
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print_num_status_bits(ARRAY_SIZE(tco_sts_bits), tco_sts, tco_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return tco_sts;
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*a = ARRAY_SIZE(tco_sts_bits);
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return tco_sts_bits;
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}
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static uint32_t reset_tco_status(void)
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uint32_t soc_reset_tco_status(void)
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{
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uint16_t tcobase = get_tcobase();
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uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS));
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@ -184,35 +79,7 @@ static uint32_t reset_tco_status(void)
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return tco_sts & tco_en;
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}
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uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); }
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void enable_gpe(uint32_t mask)
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{
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uint16_t pmbase = get_pmbase();
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uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
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gpe0_en |= mask;
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outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
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}
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void disable_gpe(uint32_t mask)
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{
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uint16_t pmbase = get_pmbase();
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uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
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gpe0_en &= ~mask;
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outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
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}
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void disable_all_gpe(void) { disable_gpe(~0); }
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static uint32_t reset_gpe_status(void)
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{
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uint16_t pmbase = get_pmbase();
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uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD)));
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outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD)));
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return gpe_sts;
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}
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static uint32_t print_gpe_sts(uint32_t gpe_sts)
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const char *const *soc_std_gpe_sts_array(size_t *a)
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{
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static const char *const gpe_sts_bits[] = {
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[0] = "GPIO_0", [1] = "GPIO_1",
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@ -233,16 +100,8 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts)
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[30] = "GPIO_30", [31] = "GPIO_31",
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};
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if (!gpe_sts)
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return gpe_sts;
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printk(BIOS_DEBUG, "GPE0a_STS: ");
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print_num_status_bits(ARRAY_SIZE(gpe_sts_bits), gpe_sts, gpe_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return gpe_sts;
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*a = ARRAY_SIZE(gpe_sts_bits);
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return gpe_sts_bits;
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}
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uint32_t clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
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void clear_pmc_status(void) { /* TODO */ }
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@ -25,6 +25,7 @@
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#include <device/pci_def.h>
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#include <elog.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/pmclib.h>
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#include <spi-generic.h>
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#include <soc/iomap.h>
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#include <soc/soc_util.h>
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@ -52,7 +53,7 @@ int southbridge_io_trap_handler(int smif)
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return 0;
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}
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void southbridge_smi_set_eos(void) { enable_smi(EOS); }
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void southbridge_smi_set_eos(void) { pmc_enable_smi(EOS); }
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global_nvs_t *smm_get_gnvs(void) { return gnvs; }
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@ -98,7 +99,7 @@ static void southbridge_smi_sleep(void)
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uint16_t pmbase = get_pmbase();
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/* First, disable further SMIs */
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disable_smi(SLP_SMI_EN);
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pmc_disable_smi(SLP_SMI_EN);
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/* Figure out SLP_TYP */
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reg32 = inl((uint16_t)(pmbase + PM1_CNT));
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@ -131,7 +132,7 @@ static void southbridge_smi_sleep(void)
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printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
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/* Disable all GPE */
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disable_all_gpe();
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pmc_disable_all_gpe();
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/* also iterates over all bridges on bus 0 */
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busmaster_disable_on_bus(0);
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@ -145,7 +146,7 @@ static void southbridge_smi_sleep(void)
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* event again. We need to set BIT13 (SLP_EN) though to make the
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* sleep happen.
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*/
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enable_pm1_control(SLP_EN);
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pmc_enable_pm1_control(SLP_EN);
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/* Make sure to stop executing code here for S3/S4/S5 */
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if (slp_typ > 1)
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@ -158,7 +159,7 @@ static void southbridge_smi_sleep(void)
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reg32 = inl((uint16_t)(pmbase + PM1_CNT));
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if (reg32 & SCI_EN) {
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/* The OS is not an ACPI OS, so we set the state to S0 */
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disable_pm1_control(SLP_EN | SLP_TYP);
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pmc_disable_pm1_control(SLP_EN | SLP_TYP);
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}
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}
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@ -237,11 +238,11 @@ static void southbridge_smi_apmc(void)
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printk(BIOS_DEBUG, "P-state control\n");
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break;
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case APM_CNT_ACPI_DISABLE:
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disable_pm1_control(SCI_EN);
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pmc_disable_pm1_control(SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
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break;
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case APM_CNT_ACPI_ENABLE:
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enable_pm1_control(SCI_EN);
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pmc_enable_pm1_control(SCI_EN);
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printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
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break;
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case APM_CNT_FINALIZE:
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@ -268,23 +269,23 @@ static void southbridge_smi_apmc(void)
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static void southbridge_smi_pm1(void)
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{
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uint16_t pm1_sts = clear_pm1_status();
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uint16_t pm1_sts = pmc_clear_pm1_status();
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/* While OSPM is not active, poweroff immediately
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* on a power button event.
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*/
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if (pm1_sts & PWRBTN_STS) {
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// power button pressed
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disable_pm1_control(-1UL);
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enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
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pmc_disable_pm1_control(-1UL);
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pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
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}
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}
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static void southbridge_smi_gpe0(void) { clear_gpe_status(); }
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static void southbridge_smi_gpe0(void) { pmc_clear_all_gpe_status(); }
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static void southbridge_smi_tco(void)
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{
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uint32_t tco_sts = clear_tco_status();
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uint32_t tco_sts = pmc_clear_tco_status();
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/* Any TCO event? */
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if (!tco_sts)
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@ -354,7 +355,7 @@ void southbridge_smi_handler(void)
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/* We need to clear the SMI status registers, or we won't see what's
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* happening in the following calls.
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*/
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smi_sts = clear_smi_status();
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smi_sts = pmc_clear_smi_status();
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/* Call SMI sub handler for each of the status bits */
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for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
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@ -23,6 +23,7 @@
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#include <cpu/x86/smm.h>
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#include <string.h>
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#include <intelblocks/pmclib.h>
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#include <soc/iomap.h>
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#include <soc/soc_util.h>
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#include <soc/pm.h>
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@ -48,10 +49,10 @@ void southcluster_smm_clear_state(void)
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}
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/* Dump and clear status registers */
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clear_smi_status();
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clear_pm1_status();
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clear_tco_status();
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clear_gpe_status();
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pmc_clear_smi_status();
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pmc_clear_pm1_status();
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pmc_clear_tco_status();
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pmc_clear_all_gpe_status();
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clear_pmc_status();
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}
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@ -60,8 +61,8 @@ void southcluster_smm_enable_smi(void)
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printk(BIOS_DEBUG, "Enabling SMIs.\n");
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/* Configure events Disable pcie wake. */
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enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
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disable_gpe(PME_B0_EN);
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pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
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pmc_disable_std_gpe(PME_B0_EN);
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/* Enable SMI generation:
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* - on APMC writes (io 0xb2)
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@ -71,7 +72,7 @@ void southcluster_smm_enable_smi(void)
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* - on TCO events
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* - on microcontroller writes (io 0x62/0x66)
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*/
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enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
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pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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