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soc/intel/apollolake: Disable XHCI LFPS power management 

Provide the option to disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: Ic603e3b919d8b443c6ede8bb5e46e2de07fcb856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Marx Wang 2020-04-07 16:58:38 +08:00 committed by Patrick Georgi
parent efc3d04af2
commit abc17d10d6
2 changed files with 39 additions and 0 deletions
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31
src/soc/intel/apollolake/chip.c
View File

@ -99,6 +99,10 @@
/* IOSF Gasket Backbone Local Clock Gating Enable */
#define IOSFGBLCGE (1 << 0)
#define CFG_XHCPMCTRL 0x80a4
/* BIT[7:4] LFPS periodic sampling for USB3 Ports */
#define LFPS_PM_DISABLE_MASK 0xFFFFFF0F
const char *soc_acpi_name(const struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
@ -829,6 +833,30 @@ static int check_xdci_enable(void)
return !!dev->enabled;
}
static void disable_xhci_lfps_pm(void)
{
struct soc_intel_apollolake_config *cfg;
cfg = config_of_soc();
if (cfg->disable_xhci_lfps_pm) {
void *addr;
const struct resource *res;
uint32_t reg;
struct device *xhci_dev = PCH_DEV_XHCI;
res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
addr = (void *)(uintptr_t)(res->base + CFG_XHCPMCTRL);
reg = read32(addr);
printk(BIOS_DEBUG, "XHCI PM: control reg=0x%x.\n", reg);
if (reg) {
reg &= LFPS_PM_DISABLE_MASK;
write32(addr, reg);
printk(BIOS_INFO, "XHCI PM: Disable xHCI LFPS as configured in devicetree.\n");
}
}
}
void platform_fsp_notify_status(enum fsp_notify_phase phase)
{
if (phase == END_OF_FIRMWARE) {
@ -876,6 +904,9 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase)
IOSFGBLCGE;
write32(cfg, reg);
}
/* Disable XHCI LFPS power management if the option in dev tree is set. */
disable_xhci_lfps_pm();
}
}

8
src/soc/intel/apollolake/chip.h
View File

@ -184,6 +184,14 @@ struct soc_intel_apollolake_config {
* the Upd parameter VtdEnable.
*/
uint8_t enable_vtd;
/* Options to disable the LFPS periodic sampling for USB3 Ports.
* Default value of PMCTRL_REG bits[7:4] is 9 which means periodic sampling
* interval is 9ms.
* Set 1 to update XHCI host MMIO BAR + PMCTRL_REG (0x80A4 bits[7:4]) to 0
* 0:Enable (default), 1:Disable.
*/
uint8_t disable_xhci_lfps_pm;
};
typedef struct soc_intel_apollolake_config config_t;