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util/ifdtool: Add support for Denverton SoC 

Denverton is a special version of IFD2 flash layout.  It defines
10GbE firmware regions (11/12) and the IE (10) region which
other IFD2 platforms do not have.  Denverton does not include the
legacy GbE region (3) or the EC region (8) which other IFD2
platforms do have.

TEST='ifdtool -p dnv coreboot.rom' and verify correct output

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Jeff Daly 2022-01-06 00:52:30 -05:00 committed by Felix Held
parent 5ff5225962
commit abd4b96eb4
3 changed files with 77 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/denverton_ns/Kconfig
View File

@ -174,4 +174,8 @@ config USE_DENVERTON_NS_FSP_CAR
endchoice endchoice
config IFD_CHIPSET
string
default "dnv"
endif ## SOC_INTEL_DENVERTON_NS endif ## SOC_INTEL_DENVERTON_NS

81
util/ifdtool/ifdtool.c
View File

@ -28,6 +28,22 @@
((const char *)(ptr) >= (base) && \ ((const char *)(ptr) >= (base) && \
(const char *)&(ptr)[1] <= (base) + (limit)) (const char *)&(ptr)[1] <= (base) + (limit))
/**
* PLATFORM_HAS_GBE_REGION - some platforms do not support the PCH GbE LAN region
*/
#define PLATFORM_HAS_GBE_REGION (platform != PLATFORM_DNV)
/*
* PLATFORM_HAS_EC_REGION - some platforms do not support the EC region
*/
#define PLATFORM_HAS_EC_REGION (ifd_version >= IFD_VERSION_2 && platform != PLATFORM_DNV)
/*
* PLATFORM_HAS_10GBE_X_REGION - some platforms have 1 or more 10GbE LAN regions
*/
#define PLATFORM_HAS_10GBE_0_REGION (platform == PLATFORM_DNV)
#define PLATFORM_HAS_10GBE_1_REGION (platform == PLATFORM_DNV)
static int ifd_version; static int ifd_version;
static int chipset; static int chipset;
static unsigned int max_regions = 0; static unsigned int max_regions = 0;
@ -237,6 +253,8 @@ static enum ich_chipset ifd2_platform_to_chipset(const int pindex)
return CHIPSET_400_SERIES_ICE_POINT; return CHIPSET_400_SERIES_ICE_POINT;
case PLATFORM_LBG: case PLATFORM_LBG:
return CHIPSET_C620_SERIES_LEWISBURG; return CHIPSET_C620_SERIES_LEWISBURG;
case PLATFORM_DNV:
return CHIPSET_DENVERTON;
default: default:
return CHIPSET_PCH_UNKNOWN; return CHIPSET_PCH_UNKNOWN;
} }
@ -255,6 +273,7 @@ static int is_platform_ifd_2(void)
PLATFORM_GLK, PLATFORM_GLK,
PLATFORM_CNL, PLATFORM_CNL,
PLATFORM_LBG, PLATFORM_LBG,
PLATFORM_DNV,
PLATFORM_ICL, PLATFORM_ICL,
PLATFORM_TGL, PLATFORM_TGL,
PLATFORM_JSL, PLATFORM_JSL,
@ -713,35 +732,55 @@ static void decode_flmstr(uint32_t flmstr)
} }
/* EC region access only available on v2+ */ /* EC region access only available on v2+ */
if (ifd_version >= IFD_VERSION_2) if (PLATFORM_HAS_EC_REGION)
printf(" EC Region Write Access: %s\n", printf(" EC Region Write Access: %s\n",
(flmstr & (1 << (wr_shift + 8))) ? (flmstr & (1 << (wr_shift + 8))) ?
"enabled" : "disabled"); "enabled" : "disabled");
printf(" Platform Data Region Write Access: %s\n", printf(" Platform Data Region Write Access: %s\n",
(flmstr & (1 << (wr_shift + 4))) ? "enabled" : "disabled"); (flmstr & (1 << (wr_shift + 4))) ? "enabled" : "disabled");
printf(" GbE Region Write Access: %s\n", if (PLATFORM_HAS_GBE_REGION) {
(flmstr & (1 << (wr_shift + 3))) ? "enabled" : "disabled"); printf(" GbE Region Write Access: %s\n",
(flmstr & (1 << (wr_shift + 3))) ? "enabled" : "disabled");
}
printf(" Intel ME Region Write Access: %s\n", printf(" Intel ME Region Write Access: %s\n",
(flmstr & (1 << (wr_shift + 2))) ? "enabled" : "disabled"); (flmstr & (1 << (wr_shift + 2))) ? "enabled" : "disabled");
printf(" Host CPU/BIOS Region Write Access: %s\n", printf(" Host CPU/BIOS Region Write Access: %s\n",
(flmstr & (1 << (wr_shift + 1))) ? "enabled" : "disabled"); (flmstr & (1 << (wr_shift + 1))) ? "enabled" : "disabled");
printf(" Flash Descriptor Write Access: %s\n", printf(" Flash Descriptor Write Access: %s\n",
(flmstr & (1 << wr_shift)) ? "enabled" : "disabled"); (flmstr & (1 << wr_shift)) ? "enabled" : "disabled");
if (PLATFORM_HAS_10GBE_0_REGION) {
printf(" 10GbE_0 Write Access: %s\n",
(flmstr & (1 << (wr_shift + 11))) ? "enabled" : "disabled");
}
if (PLATFORM_HAS_10GBE_1_REGION) {
printf(" 10GbE_1 Write Access: %s\n",
(flmstr & (1 << 4)) ? "enabled" : "disabled");
}
if (ifd_version >= IFD_VERSION_2) if (PLATFORM_HAS_EC_REGION)
printf(" EC Region Read Access: %s\n", printf(" EC Region Read Access: %s\n",
(flmstr & (1 << (rd_shift + 8))) ? (flmstr & (1 << (rd_shift + 8))) ?
"enabled" : "disabled"); "enabled" : "disabled");
printf(" Platform Data Region Read Access: %s\n", printf(" Platform Data Region Read Access: %s\n",
(flmstr & (1 << (rd_shift + 4))) ? "enabled" : "disabled"); (flmstr & (1 << (rd_shift + 4))) ? "enabled" : "disabled");
printf(" GbE Region Read Access: %s\n", if (PLATFORM_HAS_GBE_REGION) {
(flmstr & (1 << (rd_shift + 3))) ? "enabled" : "disabled"); printf(" GbE Region Read Access: %s\n",
(flmstr & (1 << (rd_shift + 3))) ? "enabled" : "disabled");
}
printf(" Intel ME Region Read Access: %s\n", printf(" Intel ME Region Read Access: %s\n",
(flmstr & (1 << (rd_shift + 2))) ? "enabled" : "disabled"); (flmstr & (1 << (rd_shift + 2))) ? "enabled" : "disabled");
printf(" Host CPU/BIOS Region Read Access: %s\n", printf(" Host CPU/BIOS Region Read Access: %s\n",
(flmstr & (1 << (rd_shift + 1))) ? "enabled" : "disabled"); (flmstr & (1 << (rd_shift + 1))) ? "enabled" : "disabled");
printf(" Flash Descriptor Read Access: %s\n", printf(" Flash Descriptor Read Access: %s\n",
(flmstr & (1 << rd_shift)) ? "enabled" : "disabled"); (flmstr & (1 << rd_shift)) ? "enabled" : "disabled");
if (PLATFORM_HAS_10GBE_0_REGION) {
printf(" 10GbE_0 Read Access: %s\n",
(flmstr & (1 << (rd_shift + 11))) ? "enabled" : "disabled");
}
if (PLATFORM_HAS_10GBE_1_REGION) {
printf(" 10GbE_1 Read Access: %s\n",
(flmstr & (1 << 0)) ? "enabled" : "disabled");
}
/* Requestor ID doesn't exist for ifd 2 */ /* Requestor ID doesn't exist for ifd 2 */
if (ifd_version < IFD_VERSION_2) if (ifd_version < IFD_VERSION_2)
@ -756,11 +795,16 @@ static void dump_fmba(const fmba_t *fmba)
decode_flmstr(fmba->flmstr1); decode_flmstr(fmba->flmstr1);
printf("FLMSTR2: 0x%08x (Intel ME)\n", fmba->flmstr2); printf("FLMSTR2: 0x%08x (Intel ME)\n", fmba->flmstr2);
decode_flmstr(fmba->flmstr2); decode_flmstr(fmba->flmstr2);
printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3); if (PLATFORM_HAS_GBE_REGION) {
decode_flmstr(fmba->flmstr3); printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3);
if (ifd_version >= IFD_VERSION_2) { decode_flmstr(fmba->flmstr3);
printf("FLMSTR5: 0x%08x (EC)\n", fmba->flmstr5); if (ifd_version >= IFD_VERSION_2) {
decode_flmstr(fmba->flmstr5); printf("FLMSTR5: 0x%08x (EC)\n", fmba->flmstr5);
decode_flmstr(fmba->flmstr5);
}
} else {
printf("FLMSTR6: 0x%08x (IE)\n", fmba->flmstr6);
decode_flmstr(fmba->flmstr6);
} }
} }
@ -1223,6 +1267,18 @@ static void lock_descriptor(const char *filename, char *image, int size)
fmba->flmstr5 |= (1 << REGION_EC) << wr_shift; fmba->flmstr5 |= (1 << REGION_EC) << wr_shift;
} }
break; break;
case PLATFORM_DNV:
/* CPU/BIOS can read descriptor and BIOS. */
fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift;
fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift;
/* CPU/BIOS can write BIOS. */
fmba->flmstr1 |= (1 << REGION_BIOS) << wr_shift;
/* ME can read descriptor and ME. */
fmba->flmstr2 |= (1 << REGION_DESC) << rd_shift;
fmba->flmstr2 |= (1 << REGION_ME) << rd_shift;
/* ME can write ME. */
fmba->flmstr2 |= (1 << REGION_ME) << wr_shift;
break;
default: default:
/* CPU/BIOS can read descriptor and BIOS. */ /* CPU/BIOS can read descriptor and BIOS. */
fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift;
@ -1642,6 +1698,7 @@ static void print_usage(const char *name)
" aplk - Apollo Lake\n" " aplk - Apollo Lake\n"
" cnl - Cannon Lake\n" " cnl - Cannon Lake\n"
" lbg - Lewisburg PCH\n" " lbg - Lewisburg PCH\n"
" dnv - Denverton\n"
" ehl - Elkhart Lake\n" " ehl - Elkhart Lake\n"
" glk - Gemini Lake\n" " glk - Gemini Lake\n"
" icl - Ice Lake\n" " icl - Ice Lake\n"
@ -1899,6 +1956,8 @@ int main(int argc, char *argv[])
platform = PLATFORM_CNL; platform = PLATFORM_CNL;
} else if (!strcmp(optarg, "lbg")) { } else if (!strcmp(optarg, "lbg")) {
platform = PLATFORM_LBG; platform = PLATFORM_LBG;
} else if (!strcmp(optarg, "dnv")) {
platform = PLATFORM_DNV;
} else if (!strcmp(optarg, "ehl")) { } else if (!strcmp(optarg, "ehl")) {
platform = PLATFORM_EHL; platform = PLATFORM_EHL;
} else if (!strcmp(optarg, "glk")) { } else if (!strcmp(optarg, "glk")) {

3
util/ifdtool/ifdtool.h
View File

@ -45,6 +45,7 @@ enum ich_chipset {
CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP) CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP)
* variants onwards */ * variants onwards */
CHIPSET_C620_SERIES_LEWISBURG, CHIPSET_C620_SERIES_LEWISBURG,
CHIPSET_DENVERTON,
}; };
enum platform { enum platform {
@ -59,6 +60,7 @@ enum platform {
PLATFORM_TGL, PLATFORM_TGL,
PLATFORM_ADL, PLATFORM_ADL,
PLATFORM_IFD2, PLATFORM_IFD2,
PLATFORM_DNV,
}; };
#define LAYOUT_LINELEN 80 #define LAYOUT_LINELEN 80
@ -171,6 +173,7 @@ typedef struct {
uint32_t flmstr3; uint32_t flmstr3;
uint32_t flmstr4; uint32_t flmstr4;
uint32_t flmstr5; uint32_t flmstr5;
uint32_t flmstr6;
} __attribute__((packed)) fmba_t; } __attribute__((packed)) fmba_t;
// processor strap // processor strap