Apply cache-as-ram conditionally on socket mPGA604

The socket mPGA604 is for P4 Xeon which to my knowledge is always
HT-enabled. I assume the existing usage of car/cache_as_ram.inc
on socket_mPGA604, namely the Tyan S2735, as broken.

Existing car/cache_as_ram.inc has invalid SIPI vector and it does
not initialise AP CPU's to activate L2 cache.

Other mPGA604 boards are not affected, as they have not been
converted to CAR.

Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/607
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/x86/Makefile.inc

@@ -193,13 +193,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc
 endif
 
 crt0s += $(cpu_incs)
-
+crt0s += $(cpu_incs-y)
-#
-# FIXME move to CPU_INTEL_SOCKET_MPGA604
-#
-ifeq ($(CONFIG_BOARD_TYAN_S2735),y)
-crt0s += $(src)/cpu/intel/car/cache_as_ram.inc
-endif
 
 ifeq ($(CONFIG_LLSHELL),y)
 crt0s += $(src)/arch/x86/llshell/llshell.inc

src/cpu/intel/socket_mPGA604/Kconfig

@@ -1,5 +1,10 @@
 config CPU_INTEL_SOCKET_MPGA604
 	bool
+
+if CPU_INTEL_SOCKET_MPGA604
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+	def_bool y
 	select CPU_INTEL_MODEL_F2X
 	select CPU_INTEL_MODEL_F3X
 	select CPU_INTEL_MODEL_F4X
@@ -13,4 +18,14 @@ config CPU_INTEL_SOCKET_MPGA604
 config SSE2
 	bool
 	default n
-	depends on CPU_INTEL_SOCKET_MPGA604
+
+config DCACHE_RAM_BASE
+	hex
+	default 0x0ffafc000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x4000
+
+endif # CPU_INTEL_SOCKET_MPGA604
+

src/cpu/intel/socket_mPGA604/Makefile.inc

@@ -10,3 +10,5 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
+cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+