src: Remove unused '#include <cpu/x86/smm.h>'

Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/haswell/haswell_init.c

@@ -13,7 +13,6 @@
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/name.h>
-#include <cpu/x86/smm.h>
 #include <delay.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <southbridge/intel/lynxpoint/pch.h>

src/drivers/elog/gsmi.c

@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
-#include <cpu/x86/smm.h>
 #include <elog.h>
 
 #define GSMI_RET_SUCCESS		0x00

src/drivers/intel/fsp1_1/car.c

@@ -6,7 +6,6 @@
 #include <console/console.h>
 #include <commonlib/helpers.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/smm.h>
 #include <fsp/car.h>
 #include <fsp/util.h>
 #include <program_loading.h>

src/drivers/intel/fsp1_1/ramstage.c

@@ -3,7 +3,6 @@
 #include <bootmode.h>
 #include <acpi/acpi.h>
 #include <console/console.h>
-#include <cpu/x86/smm.h>
 #include <fsp/ramstage.h>
 #include <fsp/util.h>
 #include <lib.h>

src/drivers/spi/spi_flash.c

@@ -4,7 +4,6 @@
 #include <boot_device.h>
 #include <boot/coreboot_tables.h>
 #include <console/console.h>
-#include <cpu/x86/smm.h>
 #include <string.h>
 #include <spi-generic.h>
 #include <spi_flash.h>

src/mainboard/google/stout/ec.c

@@ -4,7 +4,6 @@
 #include <bootmode.h>
 #include <types.h>
 #include <console/console.h>
-#include <cpu/x86/smm.h>
 #include <ec/quanta/it8518/ec.h>
 #include <device/device.h>
 #include <southbridge/intel/bd82x6x/pch.h>

src/northbridge/intel/haswell/northbridge.c

@@ -11,7 +11,6 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <cpu/x86/smm.h>
 #include <boot/tables.h>
 
 #include "chip.h"

src/soc/intel/apollolake/acpi.c

@@ -8,7 +8,6 @@
 #include <assert.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
-#include <cpu/x86/smm.h>
 #include <gpio.h>
 #include <intelblocks/acpi.h>
 #include <intelblocks/pmclib.h>

src/soc/intel/apollolake/romstage.c

@@ -9,7 +9,6 @@
 #include <console/console.h>
 #include <cpu/x86/pae.h>
 #include <delay.h>
-#include <cpu/x86/smm.h>
 #include <device/pci_def.h>
 #include <device/resource.h>
 #include <fsp/api.h>

src/soc/intel/baytrail/northcluster.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>

src/soc/intel/braswell/southcluster.c

@@ -8,7 +8,6 @@
 #include <bootstate.h>
 #include "chip.h"
 #include <console/console.h>
-#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>

src/soc/intel/broadwell/cpu.c

@@ -14,7 +14,6 @@
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/name.h>
-#include <cpu/x86/smm.h>
 #include <delay.h>
 #include <intelblocks/cpulib.h>
 #include <soc/cpu.h>

src/soc/intel/broadwell/finalize.c

@@ -3,7 +3,6 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <console/post_codes.h>
-#include <cpu/x86/smm.h>
 #include <reg_script.h>
 #include <spi-generic.h>
 #include <soc/pci_devs.h>

src/soc/intel/denverton_ns/romstage.c

@@ -6,7 +6,6 @@
 #include <cf9_reset.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/smm.h>
 #include <device/pci_ops.h>
 #include <soc/fiamux.h>
 #include <device/mmio.h>

src/soc/intel/skylake/cpu.c

@@ -13,7 +13,6 @@
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/name.h>
-#include <cpu/x86/smm.h>
 #include <cpu/intel/smm_reloc.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>

src/southbridge/intel/common/pmutil.c

@@ -3,7 +3,6 @@
 #include <types.h>
 #include <console/console.h>
 #include <device/pci_def.h>
-#include <cpu/x86/smm.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/common/gpio.h>