soc/intel/apollolake: revert CPU MP init prior to FSP-S

A major regression was introduced with commit 6520e01a
(soc/intel/apollolake: Perform CPU MP Init before FSP-S Init)
where the APs execution context is taken away by FSP-S. It
appears that FSP-S is not honoring the SkipMpInit UPD because
it's been shown with some debug code that FSP-S is compeltely
hijacking the APs:

Chrome EC: Set WAKE mask to 0x00000000
Chrome EC: Set WAKE mask to 0x00000000
CBFS: 'VBOOT' located CBFS at [440000:524140)
CBFS: Locating 'vbt.bin'
CBFS: Found @ offset 2e700 size 1a00
Running FSPS in 4 secs.. 315875 4315875
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
Running FSPS.. 4315875 4315875
ITSS IRQ Polarities Before:
ITSS IRQ Polarities Before:
IPC0: 0xffffeef8
IPC1: 0xffffffff
IPC2: 0xffffffff
IPC3: 0x00ffffff
ITSS IRQ Polarities After:
IPC0: 0xffffeef8
IPC1: 0x4a07ffff
IPC2: 0x08000000
IPC3: 0x00a11000

This is essentially a revert of 6520e01a to fix the previous
behavior.

Change-Id: I2e136ea1757870fe69df532ba615b9bfc6dfc651
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20215
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>

src/soc/intel/apollolake/chip.c

@@ -38,6 +38,7 @@
 #include <soc/nvs.h>
 #include <soc/pci_devs.h>
 #include <spi-generic.h>
+#include <soc/cpu.h>
 #include <soc/pm.h>
 #include <soc/p2sb.h>
 #include <soc/systemagent.h>
@@ -149,7 +150,7 @@ static struct device_operations cpu_bus_ops = {
 	.read_resources = DEVICE_NOOP,
 	.set_resources = DEVICE_NOOP,
 	.enable_resources = DEVICE_NOOP,
-	.init = DEVICE_NOOP,
+	.init = apollolake_init_cpus,
 	.scan_bus = NULL,
 	.acpi_fill_ssdt_generator = generate_cpu_entries,
 };

src/soc/intel/apollolake/cpu.c

@@ -16,8 +16,6 @@
  * GNU General Public License for more details.
  */
 
-#include <assert.h>
-#include <bootstate.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
@@ -27,12 +25,10 @@
 #include <cpu/x86/mtrr.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp/api.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/msr.h>
 #include <reg_script.h>
-#include <romstage_handoff.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
@@ -109,17 +105,14 @@ static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt)
 /*
  * Do essential initialization tasks before APs can be fired up -
  *
- * Skip Pre MP init MTRR programming, as MTRRs are mirrored from BSP,
+ *  1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
- * that are set prior to ramstage.
+ *  creates the MTRR solution that the APs will use. Otherwise APs will try to
- * Real MTRRs programming are being done after resource allocation.
+ *  apply the incomplete solution as the BSP is calculating it.
- *
- * Do, FSP loading before MP Init to ensure that the FSP cmponent stored in
- * external stage cache in TSEG does not flush off due to SMM relocation
- * during MP Init stage.
  */
 static void pre_mp_init(void)
 {
-	fsps_load(romstage_handoff_is_resume());
+	x86_setup_mtrrs_with_detect();
+	x86_mtrr_check();
 }
 
 /* Find CPU topology */
@@ -201,32 +194,14 @@ static const struct mp_ops mp_ops = {
 	.post_mp_init = southbridge_smm_enable_smi,
 };
 
-static void soc_init_cpus(void *unused)
+void apollolake_init_cpus(struct device *dev)
 {
-	device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);
-	assert(dev != NULL);
-
 	/* Clear for take-off */
 	if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
 		printk(BIOS_ERR, "MP initialization failure.\n");
-}
-
-/* Ensure to re-program all MTRRs based on DRAM resource settings */
-static void soc_post_cpus_init(void *unused)
-{
-	if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0)
-		printk(BIOS_ERR, "MTRR programming failure\n");
 
 	/* Temporarily cache the memory-mapped boot media. */
 	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
 		IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
 		fast_spi_cache_bios_region();
-
-	x86_mtrr_check();
 }
-
-/*
- * Do CPU MP Init before FSP Silicon Init
- */
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL);
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL);

src/soc/intel/apollolake/include/soc/cpu.h

@@ -24,4 +24,7 @@
 /* Common Timer Copy (CTC) frequency - 19.2MHz. */
 #define CTC_FREQ		19200000
 
+struct device;
+void apollolake_init_cpus(struct device *dev);
+
 #endif /* _SOC_APOLLOLAKE_CPU_H_ */