Revert "Kconfig: Bring HEAP_SIZE to a common, large value"
This reverts commit 44a48ce7a4
.
Reason for revert: It breaks wakeup from suspend on a bunch of boards.
While this approach of eyeballing "correct" values by chipset _should_
be fixed, it should also be accompanied by compile time verification
that the memory map works out.
Since nobody seems to care enough, let's just revert this, instead of
keeping the tree broken for a bunch of configurations.
Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
parent
ab5a9f9378
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acbc491237
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@ -751,7 +751,8 @@ config RTC
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config HEAP_SIZE
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hex
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default 0x100000
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default 0x100000 if FLATTENED_DEVICE_TREE
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default 0x4000
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config STACK_SIZE
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hex
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@ -35,4 +35,7 @@ config MAX_CPUS
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default 32 if SMM_TSEG
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default 4
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config HEAP_SIZE
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default 0x8000
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endif
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@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
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select FLATTENED_DEVICE_TREE
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select SPI_SDCARD
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config HEAP_SIZE
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default 0x10000
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config MAINBOARD_DIR
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default "sifive/hifive-unleashed"
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@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config HEAP_SIZE
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hex
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default 0xc0000
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endif # NORTHBRIDGE_AMD_PI
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@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
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bool
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default n
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config HEAP_SIZE
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hex
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default 0xc0000
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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@ -157,6 +157,10 @@ config S3_VGA_ROM_RUN
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bool
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default n
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config HEAP_SIZE
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hex
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default 0xc0000
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config EHCI_BAR
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hex
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default 0xfef00000
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@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
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int
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default 1
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config HEAP_SIZE
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default 0x10000
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config STACK_SIZE
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default 0x2000
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@ -216,6 +216,11 @@ config IED_REGION_SIZE
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hex
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default 0x400000
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config HEAP_SIZE
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hex
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default 0x80000 if BMP_LOGO
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default 0x10000
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config GFX_GMA_DEFAULT_MMIO
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default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
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@ -255,6 +255,10 @@ config IFWI_FILE_NAME
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help
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Name of file to store in the IFWI region.
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config HEAP_SIZE
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hex
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default 0x8000
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config MAX_ROOT_PORTS
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int
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default 6
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@ -177,6 +177,10 @@ config IED_REGION_SIZE
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hex
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default 0x400000
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config HEAP_SIZE
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hex
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default 0x8000
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config NHLT_DMIC_1CH_16B
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bool
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depends on ACPI_NHLT
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@ -104,6 +104,10 @@ config IED_REGION_SIZE
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hex
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default 0x0
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config HEAP_SIZE
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hex
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default 0x8000
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config MAX_ROOT_PORTS
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int
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default 7
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@ -106,6 +106,10 @@ config IED_REGION_SIZE
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hex
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default 0x400000
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config HEAP_SIZE
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hex
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default 0x8000
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config MAX_ROOT_PORTS
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int
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default 8
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@ -198,6 +198,11 @@ config IED_REGION_SIZE
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hex
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default 0x400000
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config HEAP_SIZE
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hex
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default 0x80000 if BMP_LOGO
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default 0x10000
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# Intel recommends reserving the PCIe TBT root port resources as below:
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# - 42 buses
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# - 194 MiB Non-prefetchable memory
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@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
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help
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If you set this option to n, will not use native SD controller.
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config HEAP_SIZE
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hex
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default 0x80000
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config IED_REGION_SIZE
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hex
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default 0x400000
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@ -152,6 +152,10 @@ config IED_REGION_SIZE
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config INTEL_TME
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default n
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config HEAP_SIZE
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hex
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default 0x10000
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config MAX_ROOT_PORTS
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int
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default 24 if SOC_INTEL_TIGERLAKE_PCH_H
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@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
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config ECAM_MMCONF_BUS_NUMBER
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default 256
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config HEAP_SIZE
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hex
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default 0x80000
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config HPET_MIN_TICKS
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hex
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default 0x80
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@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
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hex
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default 0x7C00
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config HEAP_SIZE
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hex
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default 0x80000
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config STACK_SIZE
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hex
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default 0x4000
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@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
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hex
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default 0x7C00
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config HEAP_SIZE
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hex
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default 0x80000
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config IED_REGION_SIZE
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hex
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default 0x400000
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@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
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hex
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default 0x8c00
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config HEAP_SIZE
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hex
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default 0x80000
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config STACK_SIZE
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hex
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default 0x4000
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@ -57,4 +57,8 @@ config SBL_UTIL_PATH
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help
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Path for utils to combine SBL_ELF and bootblock
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config HEAP_SIZE
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hex
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default 0x8000
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endif
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