GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization 

Add the UPD dxio_tx_vboost_enable for PCIe optimization.
It will impact the PCIe signal integrity, need to double-confirm
the SI result after enabling this setting.

BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
     the FSP log.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris.Wang 2022-12-28 17:07:48 +08:00 committed by Martin L Roth
parent e66fcb87fe
commit ad12b4f440
3 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/amd/mendocino/chip.h
View File

@ -164,6 +164,9 @@ struct soc_amd_mendocino_config {
uint8_t usb_phy_custom; uint8_t usb_phy_custom;
struct usb_phy_config usb_phy; struct usb_phy_config usb_phy;
/* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal
Integrity is highly recommended. */
uint8_t dxio_tx_vboost_enable;
}; };
#endif /* MENDOCINO_CHIP_H */ #endif /* MENDOCINO_CHIP_H */

2
src/soc/amd/mendocino/fsp_m_params.c
View File

@ -169,6 +169,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->usb_phy_ptr = 0; mcfg->usb_phy_ptr = 0;
} }
mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable;
fsp_fill_pcie_ddi_descriptors(mcfg); fsp_fill_pcie_ddi_descriptors(mcfg);
fsp_assign_ioapic_upds(mcfg); fsp_assign_ioapic_upds(mcfg);
mb_pre_fspm(mcfg); mb_pre_fspm(mcfg);

3
src/vendorcode/amd/fsp/mendocino/FspmUpd.h
View File

@ -96,7 +96,8 @@ typedef struct __packed {
/** Offset 0x04D7**/ uint8_t UnusedUpdSpace1; /** Offset 0x04D7**/ uint8_t UnusedUpdSpace1;
/* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */ /* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */
/** Offset 0x04D8**/ uint32_t usb_phy_ptr; /** Offset 0x04D8**/ uint32_t usb_phy_ptr;
/** Offset 0x04DC**/ uint8_t UnusedUpdSpace2[292]; /** Offset 0x04DC**/ uint8_t dxio_tx_vboost_enable;
/** Offset 0x04DD**/ uint8_t UnusedUpdSpace2[291];
/** Offset 0x0600**/ uint16_t UpdTerminator; /** Offset 0x0600**/ uint16_t UpdTerminator;
} FSP_M_CONFIG; } FSP_M_CONFIG;