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soc/intel/braswell: Reserve IOAPIC and ROM resources 

The mmio resouces IOAPIC and ROM area not reserved.
Reserve IOAPIC and ROM resources.

BUG=N/A
TEST=Intel CherryHill CRB booting Embedded Linux

Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Frans Hendriks 2019-03-18 13:31:56 +01:00 committed by Nico Huber
parent bd74aaf534
commit ad5e0a8e65
1 changed files with 5 additions and 0 deletions
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5
src/soc/intel/braswell/southcluster.c
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@ -20,6 +20,7 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/ioapic.h>
#include <bootstate.h> #include <bootstate.h>
#include "chip.h" #include "chip.h"
#include <console/console.h> #include <console/console.h>
@ -74,6 +75,10 @@ static void sc_add_mmio_resources(struct device *dev)
add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
add_mmio_resource(dev, 0xfff,
0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB*KiB) + 1,
(CONFIG_COREBOOT_ROMSIZE_KB*KiB)); /* BIOS ROM */
add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */
} }
/* Default IO range claimed by the LPC device. The upper bound is exclusive. */ /* Default IO range claimed by the LPC device. The upper bound is exclusive. */