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soc/intel/meteorlake: Disable L1 substates for PCIe compliance test mode 

Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.

This patch is backported from
commit 8c46232005 (soc/intel/alderlake:
Disable L1 substates for PCIe compliance test mode).

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I490a3e8158472fdd3bbc1aec74b2658b0fab56e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71169
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-12-21 11:41:33 +05:30
parent 2585a999bb
commit ad6c407927
1 changed files with 3 additions and 1 deletions
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4
src/soc/intel/meteorlake/fsp_params.c
View File

@ -86,7 +86,9 @@ static const pci_devfn_t uart_dev[] = {
*/ */
static int get_l1_substate_control(enum L1_substates_control ctl) static int get_l1_substate_control(enum L1_substates_control ctl)
{ {
if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
ctl = L1_SS_DISABLED;
else if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
ctl = L1_SS_L1_2; ctl = L1_SS_L1_2;
return ctl - 1; return ctl - 1;
} }