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soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register 

Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2020-04-29 10:04:57 +02:00 committed by Patrick Georgi
parent 2ec1c13ac4
commit ad87d1c8b9
2 changed files with 7 additions and 9 deletions
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11
src/soc/intel/cannonlake/bootblock/pch.c
View File

@ -61,22 +61,21 @@ static uint32_t get_pmc_reg_base(void)
static void soc_config_pwrmbase(void)
{
uint32_t reg32;
uint16_t reg16;
/*
* Assign Resources to PWRMBASE
* Clear BIT 1-2 Command Register
*/
reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MEMORY);
pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
reg16 &= ~(PCI_COMMAND_MEMORY);
pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);
/* Program PWRM Base */
pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */
reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
reg32 |= PCI_COMMAND_MEMORY;
pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Enable PWRM in PMC */
reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));

5
src/soc/intel/cannonlake/graphics.c
View File

@ -48,9 +48,8 @@ void graphics_soc_init(struct device *dev)
}
/* IGD needs to Bus Master */
uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
PCI_COMMAND_IO);
/*
* GFX PEIM module inside FSP binary is taking care of graphics