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mb/google/octopus: Fix wifi configuration 

This change updates devicetree and GPIO configurations to match the
schematics:
1. pcie_rp...[2] is the one being used for wifi, thus, clk_req and
deemphasis_enable for [2] need to be set instead of [0].
2. WLAN power enable, wifi disable and PERST# GPIOs need to be
configured correctly.

BUG=b:76180142
TEST=Verified that wlan0 scan works.

Change-Id: Ic51a94902e2cac3491081ade32079e5b88719f45
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Furquan Shaikh 2018-03-28 11:53:37 -07:00
parent f5116952bb
commit ade3bc5c40
2 changed files with 18 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
View File

@ -3,20 +3,20 @@ chip soc/intel/apollolake
device lapic 0 on end
end
register "pcie_rp_clkreq_pin[0]" = "3" # wifi/bt
register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt
# Disable unused clkreq of PCIe root ports
register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# Set de-emphasis to disabled for PCIE WiFI (Thunderpeak)
# as it is required for detection
register "pcie_rp_deemphasis_enable[0]" = "0"
register "pcie_rp_deemphasis_enable[2]" = "0"
# Set de-emphasis to default (enabled) for remaining ports
register "pcie_rp_deemphasis_enable[0]" = "1"
register "pcie_rp_deemphasis_enable[1]" = "1"
register "pcie_rp_deemphasis_enable[2]" = "1"
register "pcie_rp_deemphasis_enable[3]" = "1"
register "pcie_rp_deemphasis_enable[4]" = "1"
register "pcie_rp_deemphasis_enable[5]" = "1"
@ -105,7 +105,11 @@ chip soc/intel/apollolake
device pci 0f.2 on end # - Heci3
device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 on end # - PCIe-A 0 Onboard M2 Slot(Wifi)
device pci 13.0 on
chip drivers/intel/wifi
device pci 00.0 on end
end
end # - PCIe-A 0 Onboard M2 Slot(Wifi)
device pci 13.1 off end # - PCIe-A 1
device pci 13.2 off end # - PCIe-A 2
device pci 13.3 off end # - PCIe-A 3

14
src/mainboard/google/octopus/variants/baseboard/gpio.c
View File

@ -161,17 +161,17 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */
/* PCIE_WAKE[0:3]_B */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* PCIE_WAKE0_B -- WIFI_DISABLE_L */
PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */
PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */
//TODO Reef uses PCIE_WAKE0 as GPI_SCI. Whats the difference?
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_119, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE3_B */
/* PCIE_WAKE[0:3]_B */
/* PCIE_CLKREQ[0:3]_B */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_122, 0, DEEP, DN_20K, HIZCRx0, ENPD),/* PCIE_CLKREQ2_B -- EN_PP3300_WLAN */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, TxDRxE, ENPU),/* PCIE_CLKREQ3_B */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */
/* DDI[0:1] SDA and SCL -- unused */
PAD_CFG_GPIO_HI_Z(GPIO_124, NONE, DEEP, HIZCRx0, DISPUPD),/* HV_DDI0_DDC_SDA -- unused */
@ -218,7 +218,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 0, DEEP, NONE, HIZCRx0, ENPD), /* AVS_I2S1_SDI */
PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, SAME), /* AVS_I2S2_BCLK */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */
@ -234,7 +234,7 @@ static const struct pad_config gpio_table[] = {
/* SCC COMMUNITY GPIOS */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_176, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_ALERTB */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_177, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_CLK */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* SMB_DATA */
PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_189, 0, DEEP, NONE, TxDRxE, DISPUPD), /* OSC_CLK_OUT_0 */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */
@ -275,6 +275,10 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */
/* GSPI0_MOSI */
PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */
/* Enable power to wifi early in bootblock and de-assert PERST#. */
PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */
PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
};
const struct pad_config *__attribute__((weak))