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northbridge/amd: Update 00670F00 asl for reduced hardware 

Remove the language associated with the Carrizo Gfx PCIe bridges.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit cc32b09b0f0137c11d82f35274ca33e013f73748)

Change-Id: I8b67a646f98667d500fcee5da8389c10483488da
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17144
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Marshall Dawson 2016-10-14 17:57:08 -04:00 committed by Martin Roth
parent aa31f999e9
commit ade7800ec6
1 changed files with 1 additions and 35 deletions
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36
src/northbridge/amd/pi/00670F00/acpi/northbridge.asl
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@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -94,38 +95,3 @@ Device(PBR8) {
Return (PS8) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
/* GFX 1 */
Device(PBR9) {
Name(_ADR, 0x00030002)
} /* end PBR8 */
/* GFX 2 */
Device(PBRA) {
Name(_ADR, 0x00030003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APSA) } /* APIC mode */
Return (PSA) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
/* GFX 3 */
Device(PBRB) {
Name(_ADR, 0x00030004)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APSB) } /* APIC mode */
Return (PSB) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
/* GFX 4 */
Device(PBRC) {
Name(_ADR, 0x00030005)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APSC) } /* APIC mode */
Return (PSC) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */