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Intel model_106cx: Use symbolic names for MTRR bits 

Change-Id: I6ea5ca631c22fe870224a498b68d77d85798b3f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/637
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2012-02-15 15:55:03 +02:00 committed by Stefan Reinauer
parent 7916f4cef6
commit adf105fe45
1 changed files with 6 additions and 6 deletions
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12
src/cpu/intel/model_106cx/cache_as_ram.inc
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@ -63,14 +63,14 @@ clear_mtrrs:
/* Set Cache-as-RAM mask. */
movl $(MTRRphysMask_MSR(0)), %ecx
movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
xorl %edx, %edx
wrmsr
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
orl $(1 << 11), %eax
orl $MTRRdefTypeEn, %eax
wrmsr
/* Enable L2 cache. */
@ -113,7 +113,7 @@ clear_mtrrs:
movl $MTRRphysMask_MSR(1), %ecx
xorl %edx, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
@ -155,7 +155,7 @@ clear_mtrrs:
/* Disable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
andl $(~(1 << 11)), %eax
andl $(~MTRRdefTypeEn), %eax
wrmsr
post_code(0x31)
@ -196,7 +196,7 @@ clear_mtrrs:
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax
movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
xorl %edx, %edx
wrmsr
@ -212,7 +212,7 @@ clear_mtrrs:
/* Enable MTRR. */
movl $MTRRdefType_MSR, %ecx
rdmsr
orl $(1 << 11), %eax
orl $MTRRdefTypeEn, %eax
wrmsr
post_code(0x3b)