AGESA: Clean separation of SPI flash
To be precise, wakeup from S3 does not involve SPI writing, while preparing for it on cold power-ons currently does. For S3DataTypeMtrr storage is changed such that the first 4 bytes is the length of data stored like with the other two S3DataType. Change-Id: Id920650474530d4191075da4ef70daa66c904c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6085 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
This commit is contained in:
Kyösti Mälkki
parent
23b4f0c734
commit
adf3d6ff52
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@ -25,6 +25,8 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
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romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
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ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc
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romstage-y += heapmanager.c
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@ -35,11 +35,6 @@
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#include "s3_resume.h"
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#include "agesawrapper.h"
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#ifndef __PRE_RAM__
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#include <spi-generic.h>
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#include <spi_flash.h>
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#endif
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/* The size needs to be 4k aligned, which is the sector size of most flashes. */
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#define S3_DATA_VOLATILE_SIZE 0x6000
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#define S3_DATA_MTRR_SIZE 0x1000
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@ -85,7 +80,7 @@ void restore_mtrr(void)
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u32 pos, size;
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get_s3nv_data(S3DataTypeMTRR, &pos, &size);
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msrPtr = (UINT32 *)pos;
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msrPtr = (UINT32 *)(pos + sizeof(UINT32));
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disable_cache();
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@ -178,46 +173,24 @@ static void move_stack_high_mem(void)
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#endif
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#ifndef __PRE_RAM__
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static void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx)
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/* FIXME: Why store MTRR in SPI, just use CBMEM ? */
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static u8 mtrr_store[S3_DATA_MTRR_SIZE];
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static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
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{
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msr_t msr_data;
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msr_data = rdmsr(idx);
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#if CONFIG_AMD_SB_SPI_TX_LEN >= 8
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flash->write(flash, *p_nvram_pos, 8, &msr_data);
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*p_nvram_pos += 8;
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#else
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flash->write(flash, *p_nvram_pos, 4, &msr_data.lo);
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*p_nvram_pos += 4;
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flash->write(flash, *p_nvram_pos, 4, &msr_data.hi);
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*p_nvram_pos += 4;
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#endif
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memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data));
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*p_nvram_pos += sizeof(msr_data);
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}
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#endif
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void OemAgesaSaveMtrr(void)
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{
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#ifndef __PRE_RAM__
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msr_t msr_data;
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u32 i;
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struct spi_flash *flash;
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u32 pos, size;
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get_s3nv_data(S3DataTypeMTRR, &pos, &size);
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spi_init();
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flash = spi_flash_probe(0, 0, 0, 0);
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if (!flash) {
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printk(BIOS_DEBUG, "Could not find SPI device\n");
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return;
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}
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flash->spi->rw = SPI_WRITE_FLAG;
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spi_claim_bus(flash->spi);
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flash->erase(flash, pos, size);
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u32 nvram_pos = pos;
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u8 *nvram_pos = (u8 *) mtrr_store;
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/* Enable access to AMD RdDram and WrDram extension bits */
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msr_data = rdmsr(SYS_CFG);
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@ -225,12 +198,12 @@ void OemAgesaSaveMtrr(void)
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wrmsr(SYS_CFG, msr_data);
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/* Fixed MTRRs */
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write_mtrr(flash, &nvram_pos, 0x250);
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write_mtrr(flash, &nvram_pos, 0x258);
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write_mtrr(flash, &nvram_pos, 0x259);
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write_mtrr(&nvram_pos, 0x250);
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write_mtrr(&nvram_pos, 0x258);
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write_mtrr(&nvram_pos, 0x259);
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for (i = 0x268; i < 0x270; i++)
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write_mtrr(flash, &nvram_pos, i);
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write_mtrr(&nvram_pos, i);
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/* Disable access to AMD RdDram and WrDram extension bits */
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msr_data = rdmsr(SYS_CFG);
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@ -239,21 +212,33 @@ void OemAgesaSaveMtrr(void)
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/* Variable MTRRs */
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for (i = 0x200; i < 0x210; i++)
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write_mtrr(flash, &nvram_pos, i);
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write_mtrr(&nvram_pos, i);
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/* SYS_CFG */
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write_mtrr(flash, &nvram_pos, 0xC0010010);
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write_mtrr(&nvram_pos, 0xC0010010);
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/* TOM */
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write_mtrr(flash, &nvram_pos, 0xC001001A);
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write_mtrr(&nvram_pos, 0xC001001A);
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/* TOM2 */
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write_mtrr(flash, &nvram_pos, 0xC001001D);
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flash->spi->rw = SPI_WRITE_FLAG;
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spi_release_bus(flash->spi);
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write_mtrr(&nvram_pos, 0xC001001D);
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#if IS_ENABLED(CONFIG_SPI_FLASH)
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u32 pos, size;
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get_s3nv_data(S3DataTypeMTRR, &pos, &size);
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spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store);
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#endif
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}
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u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
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{
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#if IS_ENABLED(CONFIG_SPI_FLASH)
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u32 pos, size;
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get_s3nv_data(S3DataType, &pos, &size);
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spi_SaveS3info(pos, size, Data, DataSize);
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#endif
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return AGESA_SUCCESS;
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}
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#endif
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void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data)
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{
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AMD_CONFIG_PARAMS StdHeader;
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@ -274,41 +259,6 @@ void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data)
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}
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}
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#ifndef __PRE_RAM__
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u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
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{
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struct spi_flash *flash;
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u32 pos, size;
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get_s3nv_data(S3DataType, &pos, &size);
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spi_init();
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flash = spi_flash_probe(0, 0, 0, 0);
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if (!flash) {
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printk(BIOS_DEBUG, "Could not find SPI device\n");
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/* Dont make flow stop. */
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return AGESA_SUCCESS;
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}
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flash->spi->rw = SPI_WRITE_FLAG;
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spi_claim_bus(flash->spi);
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flash->erase(flash, pos, size);
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flash->write(flash, pos, sizeof(DataSize), &DataSize);
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u32 nvram_pos;
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for (nvram_pos = 0; nvram_pos < DataSize - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) {
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flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos));
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}
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flash->write(flash, nvram_pos + pos + 4, DataSize % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos));
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flash->spi->rw = SPI_WRITE_FLAG;
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spi_release_bus(flash->spi);
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return AGESA_SUCCESS;
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}
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#endif
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#ifdef __PRE_RAM__
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static void set_resume_cache(void)
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{
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@ -33,4 +33,6 @@ u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data);
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void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data);
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void OemAgesaSaveMtrr (void);
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void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);
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#endif
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@ -0,0 +1,54 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <spi-generic.h>
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#include <spi_flash.h>
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#include "s3_resume.h"
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void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
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{
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struct spi_flash *flash;
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spi_init();
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flash = spi_flash_probe(0, 0, 0, 0);
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if (!flash) {
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printk(BIOS_DEBUG, "Could not find SPI device\n");
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/* Dont make flow stop. */
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return;
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}
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flash->spi->rw = SPI_WRITE_FLAG;
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spi_claim_bus(flash->spi);
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flash->erase(flash, pos, size);
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flash->write(flash, pos, sizeof(len), &len);
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u32 nvram_pos;
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for (nvram_pos = 0; nvram_pos < len - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) {
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flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos));
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}
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flash->write(flash, nvram_pos + pos + 4, len % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos));
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flash->spi->rw = SPI_WRITE_FLAG;
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spi_release_bus(flash->spi);
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return;
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}
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@ -16,7 +16,7 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
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ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
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romstage-y += early_setup.c
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ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c
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romstage-y += imc.c
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@ -31,7 +31,7 @@ ramstage-y += reset.c
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ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c
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ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c
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ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
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romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c
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