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google/panther: general cleanup, file organization (non-functional) 

acpi_tables.c: consolidate/organize headers
chromeos.c: consolidate/organize headers; move header, #defines outside
of #ifdef
fadt.c: organize headers
gpio.h: rename include guard; add comment to trailing #endif
had_verb.h: add include guard; replace manual array size calculation with std
header macro
lan.c: remove conditional header inclusion; organize headers; remove
pre-processor directive indentations
mainboard.c: remove conditional header inclusion; organize headers; replace
spaced indentations with tab(s); add comment to trailing #endif
onboard.h: move fn prototype after #defines; add comment to trailing #endif
romstage.c: consolidate/organize headers
smihandler.c: organize headers; remove commented-out/dead code; add comment
to trailing #endif
thermal.h: add comment to trailing #endif

Change-Id: Iadafdd1092108c3f52435831fa0103f2457066f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/6270
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Matt DeVillier 2014-07-13 18:51:28 -05:00 committed by Edward O'Callaghan
parent 1f9653a1bc
commit ae141dd91b
11 changed files with 58 additions and 141 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
src/mainboard/google/panther/acpi_tables.c
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@ -17,31 +17,30 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <string.h>
#include <types.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <ec/google/chromeec/ec.h>
#include <southbridge/intel/lynxpoint/nvs.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include "thermal.h"
extern const unsigned char AmlCode[];
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/nvs.h>
#include "thermal.h"
static void acpi_update_thermal_table(global_nvs_t *gnvs)
{
gnvs->f4of = FAN4_THRESHOLD_OFF;

7
src/mainboard/google/panther/chromeos.c
View File

@ -18,11 +18,12 @@
*/
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <vendorcode/google/chromeos/chromeos.h>
#define GPIO_SPI_WP 58
#define GPIO_REC_MODE 12
@ -31,13 +32,11 @@
#define FLAG_REC_MODE 1
#define FLAG_DEV_MODE 2
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
#define GPIO_COUNT 6
#define ACTIVE_LOW 0
#define ACTIVE_HIGH 1
#ifndef __PRE_RAM__
static void fill_lb_gpio(struct lb_gpio *gpio, int num,
int polarity, const char *name, int force)
{

2
src/mainboard/google/panther/fadt.c
View File

@ -18,9 +18,9 @@
*/
#include <string.h>
#include <device/pci.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)

6
src/mainboard/google/panther/gpio.h
View File

@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef FALCO_GPIO_H
#define FALCO_GPIO_H
#ifndef PANTHER_GPIO_H
#define PANTHER_GPIO_H
struct pch_lp_gpio_map;
@ -121,4 +121,4 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
LP_GPIO_END
};
#endif
#endif /* PANTHER_GPIO_H */

9
src/mainboard/google/panther/hda_verb.h
View File

@ -17,6 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef HDA_VERB_H
#define HDA_VERB_H
#include <stdlib.h>
static const u32 mainboard_cim_verb_data[] = {
/* coreboot specific header */
0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283
@ -109,4 +114,6 @@ static const u32 mainboard_pc_beep_verbs[] = {
};
static const u32 mainboard_pc_beep_verbs_size =
sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
ARRAY_SIZE(mainboard_pc_beep_verbs);
#endif /* HDA_VERB_H */

13
src/mainboard/google/panther/lan.c
View File

@ -17,18 +17,15 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <cbfs.h>
#include <string.h>
#include <types.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/fmap.h>
#else
#include <cbfs.h>
#endif
#include "onboard.h"
static unsigned int search(char *p, char *a, unsigned int lengthp,
@ -142,11 +139,11 @@ void lan_init(void)
u16 io_base = 0;
struct device *ethernet_dev = NULL;
#if CONFIG_CHROMEOS
#if CONFIG_CHROMEOS
char **vpd_region_ptr = NULL;
search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr);
search_address = (unsigned long)(*vpd_region_ptr);
#else
#else
void *vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin",
CBFS_TYPE_RAW, &search_length);
if (vpd_file) {
@ -155,7 +152,7 @@ void lan_init(void)
search_length = -1;
search_address = 0;
}
#endif
#endif
/* Get NIC's IO base address */
ethernet_dev = dev_find_device(PANTHER_NIC_VENDOR_ID,

32
src/mainboard/google/panther/mainboard.c
View File

@ -18,25 +18,24 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <smbios.h>
#include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
#include <string.h>
#include <types.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <x86emu/x86emu.h>
#include "hda_verb.h"
#include "onboard.h"
#include <southbridge/intel/lynxpoint/pch.h>
void mainboard_suspend_resume(void)
{
@ -50,7 +49,7 @@ static int int15_handler(void)
int res = 0;
printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
__func__, X86_AX, X86_BX, X86_CX, X86_DX);
__func__, X86_AX, X86_BX, X86_CX, X86_DX);
switch (X86_AX) {
case 0x5f34:
@ -116,19 +115,19 @@ static int int15_handler(void)
default:
/* Interrupt was not handled */
printk(BIOS_DEBUG,
"Unknown INT15 5f70 function: 0x%02x\n",
"Unknown INT15 5f70 function: 0x%02x\n",
((X86_CX >> 8) & 0xff));
break;
}
break;
default:
default:
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
break;
}
return res;
}
#endif
#endif /* CONFIG_VGA_ROM_RUN */
/* Audio Setup */
@ -167,4 +166,3 @@ static void mainboard_enable(device_t dev)
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

8
src/mainboard/google/panther/onboard.h
View File

@ -1,10 +1,6 @@
#ifndef __MAINBOARD_ONBOARD_H
#define __MAINBOARD_ONBOARD_H
#ifndef __ACPI__
void lan_init(void);
#endif
/* defines for programming the MAC address */
#define PANTHER_NIC_VENDOR_ID 0x10EC
#define PANTHER_NIC_DEVICE_ID 0x8168
@ -18,4 +14,8 @@ void lan_init(void);
/* WLAN wake is GPIO 10 */
#define PANTHER_WLAN_WAKE_GPIO 10
#ifndef __ACPI__
void lan_init(void);
#endif
#endif /* __MAINBOARD_ONBOARD_H */

8
src/mainboard/google/panther/romstage.c
View File

@ -18,19 +18,19 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cbfs.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8772f/it8772f.h>
#include "gpio.h"
#include "superio/ite/it8772f/it8772f.h"
#include "superio/ite/common/ite.h"
#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)

91
src/mainboard/google/panther/smihandler.c
View File

@ -20,12 +20,12 @@
#include <arch/io.h>
#include <console/console.h>
#include <cpu/intel/haswell/haswell.h>
#include <cpu/x86/smm.h>
#include <northbridge/intel/haswell/haswell.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <southbridge/intel/lynxpoint/nvs.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <northbridge/intel/haswell/haswell.h>
#include <cpu/intel/haswell/haswell.h>
#include <elog.h>
/* GPIO46 controls the WLAN_DISABLE_L signal. */
@ -49,82 +49,9 @@ int mainboard_io_trap_handler(int smif)
* For now, we force the return value to 0 and log all traps to
* see what's going on.
*/
//gnvs->smif = 0;
return 1;
}
#if 0
static u8 mainboard_smi_ec(void)
{
u8 cmd = 0;// google_chromeec_get_event();
#if CONFIG_ELOG_GSMI
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
#endif
return cmd;
}
#endif
/* gpi_sts is GPIO 47:32 */
void mainboard_smi_gpi(u32 gpi_sts)
{
#if 0
if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
/* Process all pending events */
while (mainboard_smi_ec() != 0);
}
#endif
}
void mainboard_smi_sleep(u8 slp_typ)
{
/* Disable USB charging if required */
switch (slp_typ) {
case 3:
//if (smm_get_gnvs()->s3u0 == 0)
// google_chromeec_set_usb_charge_mode(
// 0, USB_CHARGE_MODE_DISABLED);
//if (smm_get_gnvs()->s3u1 == 0)
// google_chromeec_set_usb_charge_mode(
// 1, USB_CHARGE_MODE_DISABLED);
/* Prevent leak from standby rail to WLAN rail in S3. */
//set_gpio(GPIO_WLAN_DISABLE_L, 0);
/* Disable LTE */
//set_gpio(GPIO_LTE_DISABLE_L, 0);
/* Enable wake events */
//google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case 5:
//if (smm_get_gnvs()->s5u0 == 0)
// google_chromeec_set_usb_charge_mode(
// 0, USB_CHARGE_MODE_DISABLED);
//if (smm_get_gnvs()->s5u1 == 0)
// google_chromeec_set_usb_charge_mode(
// 1, USB_CHARGE_MODE_DISABLED);
/* Prevent leak from standby rail to WLAN rail in S5. */
//set_gpio(GPIO_WLAN_DISABLE_L, 0);
/* Disable LTE */
//set_gpio(GPIO_LTE_DISABLE_L, 0);
/* Enable wake events */
//google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
}
/* Disable SCI and SMI events */
//google_chromeec_set_smi_mask(0);
//google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
//while (google_chromeec_get_event() != 0);
}
#define APMC_FINALIZE 0xcb
static int mainboard_finalized = 0;
@ -144,17 +71,7 @@ int mainboard_smi_apmc(u8 apmc)
mainboard_finalized = 1;
break;
case APM_CNT_ACPI_ENABLE:
//google_chromeec_set_smi_mask(0);
/* Clear all pending events */
//while (google_chromeec_get_event() != 0);
//google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
break;
case APM_CNT_ACPI_DISABLE:
//google_chromeec_set_sci_mask(0);
/* Clear all pending events */
//while (google_chromeec_get_event() != 0);
//google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
default:
break;
}
return 0;

2
src/mainboard/google/panther/thermal.h
View File

@ -54,4 +54,4 @@
/* Tj_max value for calculating PECI CPU temperature */
#define MAX_TEMPERATURE 100
#endif
#endif /* THERMAL_H */