Allow selecting the physical USB Debug Port on AMD SB700.

The AMD SB700 allows changing the physical USB port to be used as
USB Debug Port, implement support for this.

Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the
SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use
D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices
currently, AFAICS.

Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility.

Untested, but should work.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/amd/mahogany/romstage.c

@@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

src/mainboard/asrock/939a785gmh/romstage.c

@@ -182,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

src/mainboard/asus/m4a785-m/romstage.c

@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

src/mainboard/jetway/pa78vm5/romstage.c

@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	uart_init();
 
 #if CONFIG_USBDEBUG
-	sb700_enable_usbdebug(0);
+	sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 	early_usbdebug_init();
 #endif
 

src/southbridge/amd/sb700/sb700_enable_usbdebug.c

@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,22 +26,39 @@
 #define EHCI_BAR_INDEX		0x10		/* TODO: DBUG_PRT[31:29] */
 #define EHCI_DEBUG_OFFSET	0xE0		/* Hardcoded to 0xE0 */
 
-/* Required for successful build, but currently empty. */
+#define EHCI_EOR		(EHCI_BAR + 0x20)
+#define DEBUGPORT_MISC_CONTROL	(EHCI_EOR + 0x80)
+
 void set_debug_port(unsigned int port)
 {
-	/* TODO: Allow changing the physical USB port used as Debug Port. */
+	u32 reg32;
+
+	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
+	reg32 = read32(DEBUGPORT_MISC_CONTROL);
+	reg32 &= ~(0xf << 28);
+	reg32 |= (port << 28);
+	reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
+	write32(DEBUGPORT_MISC_CONTROL, reg32);
 }
 
+/*
+ * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
+ * This code currently only supports the first one, i.e., USB Debug devices
+ * attached to physical USB ports belonging to the first EHCI device.
+ */
 static void sb700_enable_usbdebug(unsigned int port)
 {
-	device_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
+	device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
-
-	/* Select the requested physical USB port (1-15) as the Debug Port. */
-	set_debug_port(port);
 
 	/* Set the EHCI BAR address. */
 	pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
 
 	/* Enable access to the EHCI memory space registers. */
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+	/*
+	* Select the requested physical USB port (1-15) as the Debug Port.
+	* Must be called after the EHCI BAR has been set up (see above).
+	*/
+	set_debug_port(port);
 }