mb/google/dedede/var/madoo: Update DPTF setting

Add tcc, critical, passive policy, and pl values from thermal team.

BUG=b:169215576
TEST=build and verify by thermal tool

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I4f61eaa7eab2b86b04ff0541886621afb3082b1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
John Su 2020-09-28 16:12:26 +08:00 committed by Patrick Georgi
parent 49d74de969
commit ae763de649
1 changed files with 27 additions and 0 deletions

View File

@ -53,7 +53,34 @@ chip soc/intel/jasperlake
},
},
}"
register "power_limits_config" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 20,
}"
register "tcc_offset" = "5" # TCC of 95C
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 65, 1000)"
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
register "controls.power_limits.pl1" = "{
.min_power = 4800,
.max_power = 6000,
.time_window_min = 1 * MSECS_PER_SEC,
.time_window_max = 1 * MSECS_PER_SEC,
.granularity = 200,}"
register "controls.power_limits.pl2" = "{
.min_power = 20000,
.max_power = 20000,
.time_window_min = 1 * MSECS_PER_SEC,
.time_window_max = 1 * MSECS_PER_SEC,
.granularity = 1000,}"
device generic 0 on end
end
end # SA Thermal device
device pci 14.0 on
chip drivers/usb/acpi
device usb 0.0 on