soc/amd/*/northbridge,root_complex: add comment about PCI BARs
Add a comment to point out that the read_resources functions aren't missing a pci_dev_read_resources call that would add the resources for the BARs of the PC device. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -114,6 +114,9 @@ static void read_resources(struct device *dev)
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early_reserved_dram_start = e->base;
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early_reserved_dram_end = e->base + e->size;
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/* The root complex has no PCI BARs implemented, so there's no need to call
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pci_dev_read_resources for it */
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/* 0x0 - 0x9ffff */
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ram_resource(dev, idx++, 0, 0xa0000 / KiB);
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@ -114,6 +114,9 @@ static void read_resources(struct device *dev)
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early_reserved_dram_start = e->base;
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early_reserved_dram_end = e->base + e->size;
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/* The root complex has no PCI BARs implemented, so there's no need to call
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pci_dev_read_resources for it */
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/* 0x0 - 0x9ffff */
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ram_resource(dev, idx++, 0, 0xa0000 / KiB);
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@ -116,6 +116,9 @@ static void read_resources(struct device *dev)
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early_reserved_dram_start = e->base;
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early_reserved_dram_end = e->base + e->size;
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/* The root complex has no PCI BARs implemented, so there's no need to call
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pci_dev_read_resources for it */
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/* 0x0 - 0x9ffff */
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ram_resource(dev, idx++, 0, 0xa0000 / KiB);
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@ -60,6 +60,9 @@ static void read_resources(struct device *dev)
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unsigned int idx = 0;
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struct resource *res;
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/* The northbridge has no PCI BARs implemented, so there's no need to call
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pci_dev_read_resources for it */
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/*
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* This MMCONF resource must be reserved in the PCI domain.
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* It is not honored by the coreboot resource allocator if it is in
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