soc/amd/*/northbridge,root_complex: add comment about PCI BARs

Add a comment to point out that the read_resources functions aren't
missing a pci_dev_read_resources call that would add the resources for
the BARs of the PC device.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2022-03-02 23:36:55 +01:00
parent b1197af7f5
commit af17f0b7ce
4 changed files with 12 additions and 0 deletions

View File

@ -114,6 +114,9 @@ static void read_resources(struct device *dev)
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* The root complex has no PCI BARs implemented, so there's no need to call
pci_dev_read_resources for it */
/* 0x0 - 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);

View File

@ -114,6 +114,9 @@ static void read_resources(struct device *dev)
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* The root complex has no PCI BARs implemented, so there's no need to call
pci_dev_read_resources for it */
/* 0x0 - 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);

View File

@ -116,6 +116,9 @@ static void read_resources(struct device *dev)
early_reserved_dram_start = e->base;
early_reserved_dram_end = e->base + e->size;
/* The root complex has no PCI BARs implemented, so there's no need to call
pci_dev_read_resources for it */
/* 0x0 - 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);

View File

@ -60,6 +60,9 @@ static void read_resources(struct device *dev)
unsigned int idx = 0;
struct resource *res;
/* The northbridge has no PCI BARs implemented, so there's no need to call
pci_dev_read_resources for it */
/*
* This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in