mb/google/auron: Drop `spd.h` from variants
Factor out common DRAM SPD definitions and relocate SPD GPIO macros. Also factor out common function definition. Drop now-empty headers. Change-Id: Id05ba6c9cea27fbad5ee831f033d0de43717847e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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@ -5,7 +5,6 @@
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#include <soc/pei_data.h>
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#include <soc/pei_wrapper.h>
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#include <soc/romstage.h>
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#include <variant/spd.h>
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#include "variant.h"
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__weak void variant_romstage_entry(struct romstage_params *rp)
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@ -11,4 +11,18 @@ int variant_smbios_data(struct device *dev, int *handle,
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void variant_romstage_entry(struct romstage_params *rp);
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void lan_init(void);
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void mainboard_fill_spd_data(struct pei_data *pei_data);
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#define SPD_LEN 256
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0b
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#define SPD_DRAM_LPDDR3 0xf1
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_ORGANIZATION 7
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#define SPD_BUS_DEV_WIDTH 8
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#define SPD_PART_OFF 128
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#define SPD_PART_LEN 18
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#endif
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@ -1,26 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_SPD_H
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#define MAINBOARD_SPD_H
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#define SPD_LEN 256
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0b
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#define SPD_DRAM_LPDDR3 0xf1
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_ORGANIZATION 7
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#define SPD_BUS_DEV_WIDTH 8
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#define SPD_PART_OFF 128
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#define SPD_PART_LEN 18
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/* Auron board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 13
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#define SPD_GPIO_BIT1 9
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#define SPD_GPIO_BIT2 47
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struct pei_data;
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void mainboard_fill_spd_data(struct pei_data *pei_data);
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#endif
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@ -9,7 +9,12 @@
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#include <soc/romstage.h>
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#include <ec/google/chromeec/ec.h>
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#include <mainboard/google/auron/ec.h>
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#include <variant/spd.h>
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#include <mainboard/google/auron/variant.h>
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/* Auron board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 13
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#define SPD_GPIO_BIT1 9
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#define SPD_GPIO_BIT2 47
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static void mainboard_print_spd_info(uint8_t spd[])
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{
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@ -1,26 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_SPD_H
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#define MAINBOARD_SPD_H
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#define SPD_LEN 256
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0b
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#define SPD_DRAM_LPDDR3 0xf1
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_ORGANIZATION 7
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#define SPD_BUS_DEV_WIDTH 8
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#define SPD_PART_OFF 128
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#define SPD_PART_LEN 18
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/* Auron board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 13
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#define SPD_GPIO_BIT1 9
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#define SPD_GPIO_BIT2 47
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struct pei_data;
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void mainboard_fill_spd_data(struct pei_data *pei_data);
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#endif
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@ -9,7 +9,12 @@
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#include <soc/romstage.h>
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#include <ec/google/chromeec/ec.h>
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#include <mainboard/google/auron/ec.h>
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#include <variant/spd.h>
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#include <mainboard/google/auron/variant.h>
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/* Auron board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 13
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#define SPD_GPIO_BIT1 9
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#define SPD_GPIO_BIT2 47
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static void mainboard_print_spd_info(uint8_t spd[])
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{
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@ -1,9 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_SPD_H
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#define MAINBOARD_SPD_H
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struct pei_data;
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void mainboard_fill_spd_data(struct pei_data *pei_data);
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#endif
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/google/auron/variant.h>
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#include <soc/pei_data.h>
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#include <variant/spd.h>
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/* Copy SPD data for on-board memory */
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void mainboard_fill_spd_data(struct pei_data *pei_data)
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@ -1,26 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_SPD_H
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#define MAINBOARD_SPD_H
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#define SPD_LEN 256
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0b
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#define SPD_DRAM_LPDDR3 0xf1
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_ORGANIZATION 7
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#define SPD_BUS_DEV_WIDTH 8
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#define SPD_PART_OFF 128
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#define SPD_PART_LEN 18
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/* Gandof board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 13
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#define SPD_GPIO_BIT1 9
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#define SPD_GPIO_BIT2 47
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struct pei_data;
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void mainboard_fill_spd_data(struct pei_data *pei_data);
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#endif
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@ -9,7 +9,12 @@
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#include <soc/romstage.h>
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#include <ec/google/chromeec/ec.h>
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#include <mainboard/google/auron/ec.h>
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#include <variant/spd.h>
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#include <mainboard/google/auron/variant.h>
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/* Gandof board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 13
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#define SPD_GPIO_BIT1 9
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#define SPD_GPIO_BIT2 47
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static void mainboard_print_spd_info(uint8_t spd[])
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{
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@ -1,27 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_SPD_H
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#define MAINBOARD_SPD_H
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#define SPD_LEN 256
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0b
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#define SPD_DRAM_LPDDR3 0xf1
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_ORGANIZATION 7
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#define SPD_BUS_DEV_WIDTH 8
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#define SPD_PART_OFF 128
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#define SPD_PART_LEN 18
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/* Lulu board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 13
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#define SPD_GPIO_BIT1 9
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#define SPD_GPIO_BIT2 47
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#define SPD_GPIO_BIT3 8
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struct pei_data;
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void mainboard_fill_spd_data(struct pei_data *pei_data);
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#endif
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@ -9,7 +9,13 @@
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#include <soc/romstage.h>
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#include <ec/google/chromeec/ec.h>
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#include <mainboard/google/auron/ec.h>
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#include <variant/spd.h>
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#include <mainboard/google/auron/variant.h>
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/* Lulu board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 13
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#define SPD_GPIO_BIT1 9
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#define SPD_GPIO_BIT2 47
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#define SPD_GPIO_BIT3 8
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static void mainboard_print_spd_info(uint8_t spd[])
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{
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@ -1,27 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_SPD_H
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#define MAINBOARD_SPD_H
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#define SPD_LEN 256
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0b
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#define SPD_DRAM_LPDDR3 0xf1
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_ORGANIZATION 7
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#define SPD_BUS_DEV_WIDTH 8
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#define SPD_PART_OFF 128
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#define SPD_PART_LEN 18
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/* Samus board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 69
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#define SPD_GPIO_BIT1 68
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#define SPD_GPIO_BIT2 67
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#define SPD_GPIO_BIT3 65
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struct pei_data;
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void mainboard_fill_spd_data(struct pei_data *pei_data);
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#endif
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@ -9,7 +9,13 @@
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#include <soc/romstage.h>
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#include <ec/google/chromeec/ec.h>
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#include <mainboard/google/auron/ec.h>
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#include <variant/spd.h>
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#include <mainboard/google/auron/variant.h>
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/* Samus board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 69
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#define SPD_GPIO_BIT1 68
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#define SPD_GPIO_BIT2 67
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#define SPD_GPIO_BIT3 65
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static void mainboard_print_spd_info(uint8_t spd[])
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{
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