mb/google/brya: Remove mainboard.asl
Use C code to generate MS0X entry and provide variant hook. BUG=b:207144468 TEST=check SSDT table has the same entry. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x148) } Else { \_SB.PCI0.STXS (0x148) } } } Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -22,7 +22,6 @@ DefinitionBlock(
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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#include "mainboard.asl"
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#if CONFIG(HAVE_WWAN_POWER_SEQUENCE)
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#include "wwan_power.asl"
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#endif
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@ -1,26 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#if CONFIG(HAVE_SLP_S0_GATE)
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/*
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* S0ix Entry/Exit Notifications
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* Called from \_SB.PEPD._DSM
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*/
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Method (MS0X, 1, Serialized)
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{
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If (Arg0 == 1) {
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/*
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* On S0ix entry, clear the SLP_S0_GATE pin, so that the rest of
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* the platform can transition to its low power state as well.
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*/
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\_SB.PCI0.CTXS(GPIO_SLP_S0_GATE);
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} Else {
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/*
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* On S0ix exit, set the SLP_S0_GATE pin, so that the rest of
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* the platform will resume from its low power state.
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*/
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\_SB.PCI0.STXS(GPIO_SLP_S0_GATE);
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}
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}
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#endif
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpigen.h>
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <drivers/tpm/cr50.h>
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@ -109,6 +110,23 @@ static void mainboard_generate_shutdown(const struct device *dev)
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}
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}
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static void mainboard_generate_s0ix_hook(void)
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{
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acpigen_write_if_lequal_op_int(ARG0_OP, 1);
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{
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if (CONFIG(HAVE_SLP_S0_GATE))
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acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE);
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variant_generate_s0ix_hook(S0IX_ENTRY);
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}
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acpigen_write_else();
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{
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if (CONFIG(HAVE_SLP_S0_GATE))
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acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE);
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variant_generate_s0ix_hook(S0IX_EXIT);
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}
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acpigen_write_if_end();
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}
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static void mainboard_fill_ssdt(const struct device *dev)
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{
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const struct device *wwan = DEV_PTR(rp6_wwan);
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@ -122,6 +140,13 @@ static void mainboard_fill_ssdt(const struct device *dev)
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}
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/* for variant to fill additional SSDT */
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variant_fill_ssdt(dev);
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acpigen_write_scope("\\_SB");
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acpigen_write_method_serialized("MS0X", 1);
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mainboard_generate_s0ix_hook();
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acpigen_write_method_end(); /* Method */
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acpigen_write_scope_end(); /* Scope */
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}
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void __weak variant_fill_ssdt(const struct device *dev)
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@ -129,6 +154,19 @@ void __weak variant_fill_ssdt(const struct device *dev)
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/* Add board-specific SSDT entries */
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}
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void __weak variant_generate_s0ix_hook(enum s0ix_entry)
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{
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/* Add board-specific MS0X entries */
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/*
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if (s0ix_entry == S0IX_ENTRY) {
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implement variant operations here
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}
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if (s0ix_entry == S0IX_EXIT) {
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implement variant operations here
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}
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*/
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}
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static void mainboard_enable(struct device *dev)
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{
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dev->ops->init = mainboard_dev_init;
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@ -25,6 +25,13 @@ bool variant_is_half_populated(void);
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void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config);
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void variant_fill_ssdt(const struct device *dev);
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enum s0ix_entry {
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S0IX_EXIT,
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S0IX_ENTRY,
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};
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void variant_generate_s0ix_hook(enum s0ix_entry);
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/* Modify devictree settings during ramstage */
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void variant_devtree_update(void);
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@ -16,5 +16,7 @@
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#define GPIO_EC_IN_RW GPP_F18
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/* GPIO IRQ for tight timestamps */
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#define EC_SYNC_IRQ GPD2_IRQ
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/* GPP_H18 used as dummy here since nissa not selected HAVE_SLP_S0_GATE */
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#define GPIO_SLP_S0_GATE GPP_H18
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#endif /* __BASEBOARD_GPIO_H__ */
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