trogdor: Modify DDR training to use mrc_cache

Currently, trogdor devices have a section RO_DDR_TRAINING that is used
to store memory training data.  Changing so that we reuse the same
mrc_cache API as x86 platforms.  This requires renaming
RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the
fmap table.

BUG=b:150502246
BRANCH=None
TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage
     Make sure that first boot after flashing does memory training
     and next boot does not.
     Boot into recovery two consecutive times and make sure memory
     training occurs on both boots.

Change-Id: I16d429119563707123d538738348c7c4985b7b52
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/lib/Makefile.inc

@@ -100,6 +100,7 @@ ramstage-y += romstage_handoff.c
 romstage-y += romstage_handoff.c
 romstage-y += selfboot.c
 romstage-y += stack.c
+romstage-y += rtc.c
 ramstage-y += rtc.c
 
 romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c

src/mainboard/google/trogdor/chromeos.fmd

@@ -2,20 +2,19 @@
 
 FLASH@0x0 8M {
 	WP_RO 4M {
-		RO_SECTION 0x3c4000 {
+		RO_SECTION 0x3e4000 {
 			BOOTBLOCK 96K
 			COREBOOT(CBFS)
-			FMAP@0x3c0000 0x1000
+			FMAP@0x3e0000 0x1000
 			GBB 0x2f00
 			RO_FRID 0x100
 		}
 		RO_VPD(PRESERVE)
-		RO_DDR_TRAINING(PRESERVE) 8K
 	}
 
 	RW_VPD(PRESERVE) 32K
 	RW_NVRAM(PRESERVE) 16K
-	RW_DDR_TRAINING(PRESERVE) 8K
+	RW_MRC_CACHE(PRESERVE) 8K
 	RW_ELOG(PRESERVE) 4K
 	RW_SHARED 4K {
 		SHARED_DATA

src/soc/qualcomm/common/include/soc/qclib_common.h

@@ -11,7 +11,6 @@
 #define QCLIB_TE_NAME_LENGTH 24
 
 /* FMAP_REGION names */
-#define QCLIB_FR_DDR_TRAINING_DATA "RO_DDR_TRAINING"
 #define QCLIB_FR_LIMITS_CFG_DATA   "RO_LIMITS_CFG"
 
 /* TE_NAME (table entry name) */

src/soc/qualcomm/common/qclib.c

@@ -3,12 +3,14 @@
 #include <console/cbmem_console.h>
 #include <cbmem.h>
 #include <boardid.h>
+#include <bootmode.h>
 #include <string.h>
 #include <fmap.h>
 #include <assert.h>
 #include <arch/mmu.h>
 #include <cbfs.h>
 #include <console/console.h>
+#include <mrc_cache.h>
 #include <soc/mmu.h>
 #include <soc/mmu_common.h>
 #include <soc/qclib_common.h>
@@ -16,6 +18,8 @@
 #include <security/vboot/misc.h>
 #include <vb2_api.h>
 
+#define QCLIB_VERSION 0
+
 struct qclib_cb_if_table qclib_cb_if_table = {
 	.magic = QCLIB_MAGIC_NUMBER,
 	.version = QCLIB_INTERFACE_VERSION,
@@ -70,8 +74,15 @@ static void write_table_entry(struct qclib_cb_if_table_entry *te)
 
 	} else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name,
 			sizeof(te->name))) {
-
-		assert(fmap_overwrite_area(QCLIB_FR_DDR_TRAINING_DATA,
+		/*
+		 * Don't store training data if we're in recovery mode
+		 * because we always want to retrain due to
+		 * possibility of RW training data possibly being
+		 * updated to a different format.
+		 */
+		if (vboot_recovery_mode_enabled())
+			return;
+		assert(!mrc_cache_stash_data(MRC_TRAINING_DATA, QCLIB_VERSION,
 					     (const void *)te->blob_address, te->size));
 
 	} else if (!strncmp(QCLIB_TE_LIMITS_CFG_DATA, te->name,
@@ -112,7 +123,7 @@ __weak int qclib_soc_blob_load(void) { return 0; }
 void qclib_load_and_run(void)
 {
 	int i;
-	ssize_t ssize;
+	ssize_t data_size;
 	struct mmu_context pre_qclib_mmu_context;
 
 	/* zero ddr_information SRAM region, needs new data each boot */
@@ -127,13 +138,23 @@ void qclib_load_and_run(void)
 	/* output area, QCLib fills in DDR details */
 	qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0);
 
+	/*
+	 * We never want to use training data when booting into
+	 * recovery mode.
+	 */
+	if (vboot_recovery_mode_enabled()) {
+		memset(_ddr_training, 0, REGION_SIZE(ddr_training));
+	} else {
 		/* Attempt to load DDR Training Blob */
-	ssize = fmap_read_area(QCLIB_FR_DDR_TRAINING_DATA, _ddr_training,
-		REGION_SIZE(ddr_training));
-	if (ssize < 0)
-		goto fail;
+		data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION,
+						   _ddr_training, REGION_SIZE(ddr_training));
+		if (data_size < 0) {
+			printk(BIOS_ERR, "Unable to load previous training data.\n");
+			memset(_ddr_training, 0, REGION_SIZE(ddr_training));
+		}
+	}
 	qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA,
-				 _ddr_training, ssize, 0);
+				 _ddr_training, REGION_SIZE(ddr_training), 0);
 
 	/* hook for SoC specific binary blob loads */
 	if (qclib_soc_blob_load()) {

src/soc/qualcomm/sc7180/Kconfig

@@ -17,6 +17,7 @@ config SOC_QUALCOMM_SC7180
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select MAINBOARD_FORCE_NATIVE_VGA_INIT
 	select HAVE_LINEAR_FRAMEBUFFER
+	select CACHE_MRC_SETTINGS
 
 if SOC_QUALCOMM_SC7180
 
@@ -29,6 +30,7 @@ config VBOOT
 	select VBOOT_RETURN_FROM_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_BOOTBLOCK
+	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 
 config SC7180_QSPI
 	bool

src/soc/qualcomm/sdm845/Kconfig

@@ -9,6 +9,7 @@ config SOC_QUALCOMM_SDM845
 	select GENERIC_GPIO_LIB
 	select ARM64_USE_ARCH_TIMER
 	select SOC_QUALCOMM_COMMON
+	select CACHE_MRC_SETTINGS
 
 if SOC_QUALCOMM_SDM845
 
@@ -21,6 +22,7 @@ config VBOOT
 	select VBOOT_RETURN_FROM_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_BOOTBLOCK
+	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 
 config SDM845_QSPI
 	bool