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mb/google/drallion/variants/drallion: Adjust all I2C CLK to meet spec 

After adjustment on Drallion
Touch Pad CLK: 393 KHz
Touch Screen CLK: 381 KHz
H1 CLK: 391 KHz

BUG=b:144245601
BRANCH=master
TEST=emerge-drallion coreboot chromeos-bootimage
     measure by scope with drallion.

Change-Id: Id669d7199bc6ed4b55d7542f095c6c8baf00f984
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37230
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Su 2019-11-26 10:39:45 +08:00 committed by Patrick Georgi
parent d9105d98b7
commit afd687f71f
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/google/drallion/variants/drallion/devicetree.cb
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@ -176,20 +176,20 @@ chip soc/intel/cannonlake
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 52,
.fall_time_ns = 110,
.rise_time_ns = 180,
.fall_time_ns = 200,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 52,
.fall_time_ns = 110,
.rise_time_ns = 30,
.fall_time_ns = 80,
.data_hold_time_ns = 330,
},
.i2c[4] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 36,
.fall_time_ns = 99,
.rise_time_ns = 30,
.fall_time_ns = 60,
},
}"