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amd/stoneyridge: Remove CONFIG_LOGICAL_CPUS setup 

Delete the check for sibling cores and the programming of CPUID HTT
and CmpLegacy back-door bits.  The code has no effect on modern
Family 15h APUs.  The bits being modified come up set out of reset.

Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson 2017-09-04 17:10:50 -06:00 committed by Martin Roth
parent 06766c1efa
commit b00ba2ae6b
1 changed files with 0 additions and 20 deletions
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20
src/soc/amd/stoneyridge/model_15_init.c
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@ -37,9 +37,6 @@ static void model_15_init(device_t dev)
u8 i;
msr_t msr;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
u32 siblings;
#endif
disable_cache();
/* Enable access to AMD RdDram and WrDram extension bits */
@ -71,31 +68,14 @@ static void model_15_init(device_t dev)
for (i = 0 ; i < 6 ; i++)
wrmsr(MCI_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);